ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
to report the transmit under-run data out.
[5]
RXOVIEN
Receive FIFO Overrun Interrupt Enable
0 = Receive FIFO overrun interrupt Disabled.
1 = Receive FIFO overrun interrupt Enabled.
[4]
RXTOIEN
Slave Receive Time-out Interrupt Enable
0 = Receive time-out interrupt Disabled.
1 = Receive time-out interrupt Enabled.
[3]
TXTHIEN
Transmit FIFO Threshold Interrupt Enable
0 = TX FIFO threshold interrupt Disabled.
1 = TX FIFO threshold interrupt Enabled.
[2]
RXTHIEN
Receive FIFO Threshold Interrupt Enable
0 = RX FIFO threshold interrupt Disabled.
1 = RX FIFO threshold interrupt Enabled.
[1]
TXRST
Clear Transmit FIFO Buffer
0 = No effect.
1 = Clear transmit FIFO buffer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit
will be set to 1. This bit will be cleared to 0 by hardware about 3 system 3 SPI
engine clock after it is set to 1.
Note: If there is slave receive time out event, the TXRST will be set 1 when the
SPI0_SSCTL.SLVTORST, is enabled.
[0]
RXRST
Clear Receive FIFO Buffer
0 = No effect.
1 = Clear receive FIFO buffer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit
will be set to 1. This bit will be cleared to 0 by hardware about 3 system 3 SPI
engine clock after it is set to 1.
Note: If there is slave receive time out event, the RXRST will be set 1 when the
SPI0_SSCTL.SLVTORST, is enabled.
