ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 281 -
Revision 2.4
5.12 Watchdog Timer
The purpose of Watchdog Timer is to perform a system reset if software is not responding as designed.
This prevents system from hanging for an infinite period of time. The watchdog timer includes a 18-bit
free running counter with programmable time-out intervals.
Setting WDTEN enables the watchdog timer and the WDT counter starts counting up. When the
counter reaches the selected time-out interval, Watchdog timer interrupt flag IF will be set immediately
to request a WDT interrupt if the watchdog timer interrupt enable bit INTEN is set, in the meantime, a
specified delay time follows the time-out event. User must set RSTCNT (Watchdog timer reset) high to
reset the 18-bit WDT counter to prevent Watchdog timer reset before the delay time expires. RSTCNT
bit is auto cleared by hardware after WDT counter is reset. There are eight time-out intervals with
specific delay time which are selected by Watchdog timer interval select bits TOUTSEL. If the WDT
counter has not been cleared after the specific delay time expires, the watchdog timer will set
Watchdog Timer Reset Flag (RSTF) high and reset CPU. This reset will last 64 WDT clocks then CPU
restarts executing program from reset vector (0x0000 0000). RSTF will not be cleared by Watchdog
reset. User may poll WTFR by software to recognize the reset source.
If the application uses any sleep modes (calling wfi or wfe instructions), the watchdog reset may not
fully reset the M0 core due to parts of the core being un-clocked. In this case application should detect
the RSTF in boot sequence and perform a Deep Power Down (DPD) to ensure complete reset. See the
Timer driver sample code for example.
Table 5-114 Watchdog Timeout Interval Selection
TOUTSEL
Interrupt Timeout
Watchdog Reset Timeout
RSTCNT Timeout Interval
(WDT_CLK=HIRC 49.152
MHz)
RSTCNT Timeout Interval
(WDT_CLK=LXT 32kHz)
000
2
4
WDT_CLK
(2
4
+ 1024) WDT_CLK
21.2us
31.7 ms
001
2
6
WDT_CLK
(2
6
+ 1024) WDT_CLK
22.1 us
33.2 ms
010
2
8
WDT_CLK
(2
8
+ 1024) WDT_CLK
26.0 us
39 ms
011
2
10
WDT_CLK
(2
10
+ 1024) WDT_CLK
41.7 us
64 ms
100
2
12
WDT_CLK
(2
12
+ 1024) WDT_CLK
104.2 us
160 ms
101
2
14
WDT_CLK
(2
14
+ 1024) WDT_CLK
354.2 us
544 ms
110
2
16
WDT_CLK
(2
16
+ 1024) WDT_CLK
1.4 ms
2080 ms
111
2
18
WDT_CLK
(2
18
+ 1024) WDT_CLK
5.4 ms
8224 ms
11
10
01
00
HCLK/2048
LXT
HIRC
LIRC
WDT_CLK
SYSCLK->APBCLK.WDG_EN
SYSCLK->CLKSEL1.WDG_S
Figure 5-69 Watchdog Timer Clock Control
