ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 276 -
Revision 2.4
5.11.5 Register Description
Timer Control Register (TIMERn_CTL)
Register
Offset
R/W
Description
Reset Value
TMRn_CTL
0x00 R/W
Timer Control and Status Register
0x0000_0005
31
30
29
28
27
26
25
24
Reserved
CNTEN
INTEN
OPMODE[1:0]
RSTCNT
ACTSTS
Reserved
23
22
21
20
19
18
17
16
Reserved
CNTDATEN
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
PSC[7:0]
Table 5-110 Timer Control and Status Register (TIMERx_CTL, address 0x400
x
*0x20).
Bits
Description
[31]
Reserved
Reserved.
[30]
CNTEN
Counter Enable Bit
0 = Stops/Suspends counting.
1 = Starts counting.
Note1: Setting CNTEN = 1 enables 24-bit counter. It continues count from last value.
Note2: This bit is auto-cleared by hardware in one-shot mode (OPMODE = 00b)
when the timer interrupt is generated (INTEN = 1b).
[29]
INTEN
Interrupt Enable Bit
0 = Disable TIMER Interrupt.
1 = Enable TIMER Interrupt.
If timer interrupt is enabled, the timer asserts its interrupt signal when the count is
equal to TIMERx_CMP.
[28:27]
OPMODE
Timer Operating Mode
0 = The timer is operating in the one-shot mode. The associated interrupt signal is
generated once (if INTEN is enabled) and CNTEN is automatically cleared by
hardware.
1 = The timer is operating in the periodic mode. The associated interrupt signal is
generated periodically (if INTEN is enabled).
2 = Reserved.
3 = The timer is operating in continuous counting mode. The associated interrupt
signal is generated when CNT = TIMERx_CMP (if INTEN is enabled); however, the
24-bit up-counter counts continuously without reset.
[26]
RSTCNT
Counter Reset Bit
Set this bit will reset the timer counter, pre-scale and also force CNTEN to 0.
0 = No effect.
1 = Reset Timer’s pre-scale counter, internal 24-bit up-counter and CNTEN bit.
