ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
To configure the SPI interface to the above specifications perform the following steps:
8) Configure the SPI1_ SSCTL register. SPI1_ SSCTL.SSLVL=1 for active high slave select, SPI1_
SSCTL.SSR.SSLTRIG=1 for level sensitive trigger.
9) Configure the SPI1_CTL register. Set SPI1_CTL.SLAVE=1 for slave mode, set SPI1_CTL.CLKP=1
for SCLK polarity idle high, set SPI1_CTL.TXNEG=1 so that data changes on falling edge of SCLK,
set SPI1_CTL.RXNEG=0 so that data is latched into device on positive edge of SCLK, set
SPI1_CTL.TXBITLEN=8 and SPI1_CTL.TXNUM=0 for a single byte transfer and finally set
SPI1_CTL.LSB=1 for LSB first transfer.
10) If SPI slave is to transmit one byte of data to the off-chip master device, write first byte to TX[0]
register. If no data to be transmitted write a dummy byte.
11) Enable the EN bit to wait for the slave select trigger input and serial clock input from the off-chip
master device to start the data transfer at the SPI interface.
-- -- Wait for SPI transfer to finish. Can be interrupt driven (if the interrupt enable SPI1_CTL.IE bit is set)
or by polling the EN bit which will be cleared to 0 by hardware automatically at end of transmission. --
12) Read out the received data from SPI1_RX0 register.
13) Go to 3) to continue another data transfer or disable the EN bit to stop data transfer.
