ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 267 -
Revision 2.4
[1]
RXNEG
Receive At Negative Edge
0 = The received data input signal is latched at the rising edge of SCLK.
1 = The received data input signal is latched at the falling edge of SCLK.
[0]
EN
Go and Busy Status
0 = Writing 0 to this bit has no effect.
1 = Writing 1 to this bit starts the transfer. This bit remains set during the
transfer and is automatically cleared after transfer finished.
NOTE
: All registers should be set before writing 1 to this EN bit. When a
transfer is in progress, writing to any register of the SPI master/slave core
has no effect.
SPI Divider Register (DIVIDER)
Register
Offset
R/W
Description
Reset Value
SPI1_CLKDIV
S 0x04 R/W
Clock Divider Register (Master Only)
0x0000_0000
31
30
29
28
27
26
25
24
CLKDIV1
23
22
21
20
19
18
17
16
CLKDIV1
15
14
13
12
11
10
9
8
CLKDIV0
7
6
5
4
3
2
1
0
CLKDIV0
Table 5-102 SPI Control and Status Register (SPI_CTL, address 0x4003_8004)
Bits
Description
[31:16]
CLKDIV1
Clock Divider 2 Register
(master only)
The value in this field is the 2
nd
frequency divider of the system clock,
PCLK, to generate the serial clock on the output SCLK. The desired
frequency is obtained according to the following equation:
2
*
)
1
2
(
+
=
DIVIDER
f
f
pclk
sclk
