ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 17 -
Revision 2.4
3.2
Pin Description
The ISD91200 is a low pin count device where many pins are configurable to alternative functions. All
General Purpose Input/Output (GPIO) pins can be configured to alternate functions as described in the
table below.
Pin No.
Pin Name
Pin Type Alt CFG Description
LQFP
64
1
NC
2
NC
3
NC
4
VCCA
P
Analog power supply.
5
VCCLDO
P
Power supply for LDO, should be connected to VCCD.
6
VLDOx
P
LDO regulator output. if used, a 1μF decoupling capacitor must be
placed. If not used then tie to VCCD.
7
PA.0
I/O
0
General purpose input/output pin; Port A, bit 0
SPI0_MISO1
O
1
2
nd
Master In, Slave Out for SPI0 interface
SPI0_SSB1
O
2
Slave Select Bar 1 for SPI0 interface
I2S0_FS
I/O
3
Frame Sync Clock for I2S interface
8
PA.1
I/O
0
General purpose input/output pin; Port A, bit 1
SPI0_MOSI0
O
1
1
st
Master Out, Slave In for SPI0 interface
I2S0_BCLK
I/O
3
Bit Clock for I2S interface
9
PA.2
I/O
0
General purpose input/output pin; Port A, bit 2
SPI0_SCLK0
I/O
1
Serial Clock for SPI 0interface
DMIC_DAT
I
2
DMIC data
I2S0_SDI
I
3
Serial Data Input for I2S interface
10
PA.3
I/O
0
General purpose input/output pin; Port A, bit 3
SPI0_SSB0
O
1
Slave Select Bar 0 for SPI0 interface
SARADC_TRIG
I
2
SARADC Trigger
I2S0_SDO
O
3
Serial Data Output for I2S interface
11
PA.4
I/O
0
General purpose input/output pin; Port A, bit 4
SPI0_MISO0
O
1
Master In, Slave Out channel 0 for SPI interface
UART0_TX
O
2
Transmit channel of UART 0
SPI1_MOSI
O
3
Master Out, Slave In for SPI1 interface
12
PA.5
I/O
0
General purpose input/output pin; Port A, bit 5
SPI0_MOSI1
O
1
2
nd
Master Out, Slave In for SPI0 interface
UART0_RX
I
2
Receive channel of UART 0
SP1_SCLK
I/O
3
Serial Clock for SPI1 interface
13
PA.6
I/O
0
General purpose input/output pin; Port A, bit 6
UART0_TX
O
1
Transmit channel of UART 0
I2C0_SDA
I/O
2
Serial Data, I2C interface
