ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
5.11 Timer Controller
5.11.1 General Timer Controller
The I91200 provides two general 24bit timer modules, TIMER0 and TIMER1. They allow the user to
implement event counting or provide timing control for applications. The timer can perform functions
such as frequency measurement, event counting, interval measurement, clock generation and delay
timing. The timer can generates an interrupt signal upon timeout and provide the current value of count
during operation.
5.11.2 Features
Independent clock source for each channel(TMR0_CLK, TMR1_CLK).
Time out period = (Period of timer clock input) * (8-bit pr 1) * (24-bit CMPDAT)
Maximum count cycle time = (1 / TMR_CLK) * (2^8) * (2^24).
Internal 24-bit up counter is readable through TIMERx_CNT (Timer Data Register).
5.11.3 Timer Controller Block Diagram
Each channel is equipped with an 8-bit pre-scale counter, a 24-bit up-counter, a 24-bit compare register
and an interrupt request signal. Refer to below figure for the timer controller block diagram. There are
five options of clock source for each channel, Figure 5-68 Clock Source of Timer Controller illustrate the
clock source control function.
24-bit up-counter
24-bit TDR
24-bit TCMPR
TMRn_CTL.CNTDATEN
Q
Q
SET
CLR
D
TMRn_INTSTS.TIF
8-bit Prescale
TMRx_CLK
TMRn_CTL.CNTEN
latch
TMRn_CTL.RSTCNT
Clear bit
Reset counter
Reset counter in
MODE=00/01
Timer Interrupt
+
-
=
Figure 5-67 Timer Controller Block Diagram
