ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 188 -
Revision 2.4
PWM Comparator Register 1-0 (PWM_CMPDAT)
Register
Offset
R/W
Description
Reset Value
PWM_CMPDAT0
0x010 R/W
PWM Comparator Register 0
0x0000_0000
PWM_CMPDAT1
0x01C R/W
PWM Comparator Register 1
0x0000_0000
PWM_CMPDAT2
0x028 R/W
PWM Comparator Register 2
0x0000_0000
PWM_CMPDAT3
0x034 R/W
PWM Comparator Register 3
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
CMP[15:8]
7
6
5
4
3
2
1
0
CMP[7:0]
Table 5-66 PWM Comparator Register (PWM_CMPDATx, address 0x400 C*x).
Bits
Description
[31:16]
Reserved
Reserved.
[15:0]
CMP
PWM Comparator Register
CMP determines the PWM duty cycle.
PWM frequency = PWM0CHx_CLK/(p1)*(clock divider)/(1);.
Duty Cycle = (CMP+1)/(1).
CMP > = PERIOD: PWM output is always high.
CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width =
(CMP+1) unit.
CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
Note:
Any write to CMP will take effect in next PWM cycle.