ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 344 -
Revision 2.4
PDMA Interrupt Status Register (PDMA_INTSTSn)
Register
Offset
R/W
Description
Reset Value
PDMA_INTSTSn
P0x24 R/W
PDMA Interrupt Status Register of Channel n
0x0000_0000
31
30
29
28
27
26
25
24
INTSTS
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
WRAPIF
7
6
5
4
3
2
1
0
Reserved
TXIF
ABTIF
Table 5-147 PDMA Interrupt Enable Status Register (PDMA_INTSTSn, address 0x500
n
*0x100)
Bits
Description
[31]
INTSTS
Interrupt Pin Status (Read Only)
This bit is the Interrupt pin status of PDMA channel.
[30:12]
Reserved
Reserved.
[11:8]
WRAPIF
Wrap Around Transfer Byte Count Interrupt Flag
These flags are set whenever the conditions for a wraparound interrupt (complete or
half complete) are met. They are cleared by writing one to the bits.
0001 = Current transfer finished flag (PDMA_CURTXCNT == 0).
0100 = Current transfer half complete flag (PDMA_CURTXCNT == PDMA_TXCNT
/2).
[7:2]
Reserved
Reserved.
[1]
TXIF
Block Transfer Done Interrupt Flag
This bit indicates that PDMA block transfer complete interrupt has been generated. It
is cleared by writing 1 to the bit.
0 = Transfer ongoing or Idle.
1 = Transfer Complete.
[0]
ABTIF
PDMA Read/Write Target Abort Interrupt Flag
This flag indicates a Target Abort interrupt condition has occurred. This condition
can happen if attempt is made to read/write from invalid or non-existent memory
space. It occurs when PDMA controller receives a bus error from AHB master. Upon
occurrence PDMA will stop transfer and go to idle state. To resume, software must
reset PDMA channel and initiate transfer again.
0 = No bus ERROR response received.
1 = Bus ERROR response received.
NOTE: This bit is cleared by writing 1 to itself.
