ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 404 -
Revision 2.4
DPWM FIFO Status Register (DPWM_STS)
Register
Offset
R/W
Description
Reset Value
DPWM_STS
0x04 R
DPWM DATA FIFO Status Register
0x0000_0002
31
30
29
28
27
26
25
24
BISTEN
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
FIFOPTR
Reserved
RXTHIF
EMPTY
FULL
Table 7-2
DPWM FIFO Status Register
(DPWM_STS, address 0x4007_0004)
Bits
Description
[31]
BISTEN
BIST Enable
0 = disable DPWM FIFO BIST testing.
1 = enable DPWM FIFO BIST testing.
DPWM FIFO can be testing by Cortex-M0
Internal use
[30:8]
Reserved
Reserved.
[7:4]
FIFOPTR
DPWM FIFO Pointer (Read Only)
The FULL bit and FIFOPOINTER indicates the field that the valid data count within
the DPWM FIFO buffer.
The Maximum value shown in FIFO_POINTER is 15. When the using level of
DPWM FIFO Buffer equal to 16, The FULL bit is set to 1.
[3]
Reserved
Reserved.
[2]
RXTHIF
DPWM FIFO Threshold Interrupt Status (Read Only)
0 = The valid data count within the DPWM FIFO buffer is larger than the setting
value of RXTH.
1 = The valid data count within the transmit FIFO buffer is less than or equal to the
setting value of RXTH.
[1]
EMPTY
FIFO Empty
0 = FIFO is not empty.
1 = FIFO is empty.
[0]
FULL
FIFO Full
0 = FIFO is not full.
1 = FIFO is full.
