ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 238 -
Revision 2.4
SPI Divider Register (SPI0_CLKDIV)
Register
Offset
R/W
Description
Reset Value
SPI0_CLKDIV
S 0x04 R/W
Clock Divider Register (Master Only)
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
DIVIDER
Table 5-92 SPI Clock Divider Register (SPI0_CLKDIV, address 0x4003_0004)
Bits
Description
[31:8]
Reserved
Reserved.
[7:0]
DIVIDER
Clock Divider Register
The value in this field is the frequency divider for generating the SPI engine
clock,Fspi_sclk, and the SPI serial clock of SPI master. The frequency is obtained
according to the following equation.
Fspi_sclk = Fspi_clockSRC / (1).
where
Fspi_clockSRC is the SPI engine clock source, which is defined in the clock control,
CLKSEL1 register.
