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COM Express™ conga-TS370

8th Generation Intel® Core™

i7, i5, i3 and Xeon processor with either QM370, HM370, or CM246 Chipset

User’s Guide

Revision 1.7

Summary of Contents for 049000

Page 1: ...COM Express conga TS370 8th Generation Intel Core i7 i5 i3 and Xeon processor with either QM370 HM370 or CM246 Chipset User s Guide Revision 1 7...

Page 2: ...PN 049103 Corrected the AMI Aptio UEFI firmware version and added note about Intel AMT support in section 2 1 Feature List Added the link configurations that are possible with customized BIOS in sect...

Page 3: ...ongatec com en licenses Search for the revision of the BIOS UEFI or Board Controller Software as shown in the POST screen or BIOS setup to get the complete product related license information To the e...

Page 4: ...rising out of or in connection with this user s guide or any other information contained herein or the use thereof Intended Audience This user s guide is intended for technically qualified personnel I...

Page 5: ...ec GmbH All rights reserved All text pictures and graphics are protected by copyrights No copying is permitted without written permission from congatec GmbH congatec GmbH has made every attempt to ens...

Page 6: ...e non conforming product freight prepaid congatec GmbH will pay for transporting the repaired or exchanged product to the customer Repaired replaced or exchanged product will be warranted for the repa...

Page 7: ...n made available to assist you If you still require assistance after visiting our website then contact our technical support department by email at support congatec com Terminology Term Description GB...

Page 8: ...32 6 1 5 USB 32 6 1 6 Gigabit Ethernet 33 6 1 7 High Definition Audio HDA 33 6 1 8 LPC Bus 33 6 1 9 I C Bus 33 6 1 10 General Purpose Serial Interface 33 6 1 11 GPIOs 34 6 1 12 Power Control 34 6 1 13...

Page 9: ...tions 48 9 2 Bootstrap Signals 70 10 System Resources 71 10 1 I O Address Assignment 71 10 1 1 LPC Bus 71 10 2 PCI Configuration Space Map 72 10 3 I2 C 73 10 4 SM Bus 73 11 BIOS Setup Description 74 1...

Page 10: ...Signal Descriptions 59 Table 19 CRT Signal Descriptions 60 Table 20 LVDS Signal Descriptions 60 Table 21 Serial ATA Signal Descriptions 61 Table 22 USB 2 0 Signal Descriptions 61 Table 23 USB 3 0 Sign...

Page 11: ...nents and is mounted onto an application specific carrier board COM modules are legacy free design no Super I O PS 2 keyboard and mouse and provide most of the functional requirements for any applicat...

Page 12: ...B 2 0 4 USB 3 1 8 USB 2 0 4 USB 3 1 8 USB 2 0 4 USB 3 1 8 USB 2 0 4 USB 3 1 SATA 6 Gbps 4 4 4 4 LVDS Yes Yes Yes Yes DP Yes Yes Yes Yes Processor TDP cTDP down 45 W 35 W 45 W 35 W 45 W 35 W 45 W 35 W...

Page 13: ...DR4 Memory ECC or Non ECC 2666 MT s dual channel ECC or non ECC 2666 MT s dual channel ECC or non ECC 2666 MT s dual channel Non ECC 2666 MT s dual channel Non ECC PCIe Lanes 8 Gen 3 8 Gen 3 8 Gen 3 8...

Page 14: ...o Technology HD hardware accelerated video decode encode processing transcode Up to three independent displays see table 7 Display Combinations and Resolutions 3x DP 1 PEG Gen 3 port x16 lanes 1x LVDS...

Page 15: ...ports only 64 bit operating systems 2 The CSM Compatibility Support Module is disabled in the BIOS setup menu by default because we recommend to operate the system in native UEFI mode 2 3 Mechanical D...

Page 16: ...limitations for pinout Type 6 dual connector 440 pins Power Rail Module Pin Current Capability Ampere Nominal Input Volts Input Range Volts Derated Input Volts Max Input Ripple 10 Hz to 20 MHz mV Max...

Page 17: ...The power consumption values were recorded during the following system states System State Description Comment S0 Minimum value Lowest frequency mode LFM with minimum core voltage during desktop idle...

Page 18: ...Core i7 9850HE 6 2 7 4 4 0 25 7 57 9 91 0 09 0 06 0 001 049104 2 x 4 GB A 1 BHCOR023 Intel Celeron G4930E 2 2 4 N A 0 27 1 25 1 48 0 09 0 06 0 001 049110 2 x 4 GB A 1 BQCOR023 Intel Xeon E 2276ML 6 2...

Page 19: ...s 4 We recommend to always have a CMOS battery present when operating the conga TS370 2 7 Environmental Specifications Temperature Operation 0 to 60 C Storage 20 to 80 C Humidity Operation 10 to 90 St...

Page 20: ...Rev 3 0 Compact Size Type 6 Pinout XDP SPI Flash 0 TPM Ethernet 10 100 1000 Intel i219LM V eDP to LVDS MUX MUX MUX DP to VGA eMMC PCIe lane 4 5 Optional Not available by default congatec Board Control...

Page 21: ...g on the environmental conditions it is subjected to For more information about this subject contact your local congatec sales representative and request the gap pad material manufacturer s specificat...

Page 22: ...22 75 4 1 CSA Dimensions 7 3 0 2 F 28 F 7 3 M2 5 x 13 mm threaded standoff for threaded version or 2 7 x 13 mm non threaded standoff for borehole version 87 29 95 96 6 21 20 31 14 5 125 58 5 76 79 117...

Page 23: ...GmbH TSCOm17 23 75 4 2 CSP Dimensions 87 14 5 31 117 76 58 5 79 M2 5 x 13 mm threaded standoff for threaded version or 2 7 x 13 mm non threaded standoff for borehole version 20 28 95 125 28 15 E E 0 6...

Page 24: ...ight 2018 congatec GmbH TSCOm17 24 75 4 3 HSP Dimensions M2 5 x 11 mm threaded standoff for threaded version or 2 7 x 11 mm non threaded standoff for borehole version 87 11 95 4 56 41 5 58 5 76 79 117...

Page 25: ...ne point to another They are often referred to as the superconductors of heat as they possess an extra ordinary heat transfer capacity and rate with almost no heat loss The thermal image below shows t...

Page 26: ...on the top side of the module and two sensors on the bottom side of the module Top Side CPU Temperature The CPU temperature sensor T00 is located in the CPU U1 This sensor measures the CPU temperature...

Page 27: ...70 offers two board temperature sensors on the bottom side of the module These sensors measure the temperature of the module and are defined in CGOS API as CGOS_TEMP_BOARD and CGOS_TEMP_BOARD_ALT resp...

Page 28: ...s six PCIe lanes on the A B connector and two PCIe lanes on the C D connector The lanes support up to 8 GTps Gen 3 speed an 8 x1 link configuration a 1 x4 2 x2 link a 4 x2 link or a 2 x4 link via a sp...

Page 29: ...below PEG LANE 0 Single Link 1x16 Link Link 1 Link 1 Link 1 Link 2 Link 3 Link 2 Double Links 2x8 Links Triple Links 1x8 2x4 Links PEG LANE 1 PEG LANE 2 PEG LANE 3 PEG LANE 4 PEG LANE 5 PEG LANE 6 PEG...

Page 30: ...4096x2160 30 Hz 24 bpp 4096x2160 30 Hz 24 bpp Option 2 DP or TMDS 4096x2304 60 Hz 24 bpp DP or TMDS 4096x2304 60 Hz 24 bpp LVDS or eDP 1920x1200 60 Hz dual LVDS mode 4096x2160 30 Hz 24 bpp 4096x2160 3...

Page 31: ...P The conga TS370 offers an LVDS eDP interface This interface is configured in the BIOS to support LVDS by default For eDP support go to Advanced Graphics Active LFP Configuration of the BIOS setup me...

Page 32: ...y space and RAID 0 1 5 10 mode Hot plug detect Note The PCH SATA controller no longer supports IDE legacy mode using I O space Therefore you need an AHCI driver 6 1 5 USB The conga TS370 offers eight...

Page 33: ...the conga TS370 module 6 1 7 High Definition Audio HDA The conga TS370 provides an HDA interface on the A B connector 6 1 8 LPC Bus The conga TS370 offers the LPC Low Pin Count bus through the Intel 3...

Page 34: ...the power is good and the module can start its onboard power sequencing Carrier board hardware must drive this signal low until all power rails and clocks are stable Releasing PWR_OK too early or not...

Page 35: ...e only around 0 8V when the 12V is applied to the module Actively driving PWR_OK high is compliant to the COM Express specification but this can cause back driving Therefore congatec recommends drivin...

Page 36: ...S settings or by system software Standard 12V Power Supply Implementation Guidelines The 12 volt input power is the sole operational power source for the conga TS370 Other required voltages are genera...

Page 37: ...n while in S3 S4 S5 In the Deep Sx state the system entry condition determines if the system context is maintained or not All power is shut off except for minimal logic which supports limited set of w...

Page 38: ...Board Information The cBC provides a rich data set of manufacturing and board information such as serial number EAN number hardware and firmware revisions and so on It also keeps track of dynamically...

Page 39: ...s additional signals and functions to further improve system management One of these signals is FAN_PWMOUT an output signal that allows system fan control using a PWM Pulse Width Modulation output Add...

Page 40: ...y themselves using the congatec system utility CGUTIL See congatec application note AN8_Create_OEM_Default_Map pdf on the congatec website for details on how to add OEM default settings to the congate...

Page 41: ...nterface To facilitate the development of battery powered mobile systems based on embedded modules congatec GmbH defined an interface for the exchange of data between a CPU module using an ACPI operat...

Page 42: ...OS API driver provides the ability to write application software that runs unmodified on all congatec CPU modules All the hardware related code is contained within the congatec embedded BIOS on the mo...

Page 43: ...uce frequency and voltage adaptively The Adaptive Thermal Monitor will remain active as long as the package temperature remains at its specified limit Therefore the Adaptive Thermal Monitor will conti...

Page 44: ...requency control This feature is also referred to as Hardware controlled Performance States HWP It is a hardware implementation of the ACPI defined Collaborative Processor Performance Control CPPC2 an...

Page 45: ...zation Technology for IA 32 Intel 64 and Intel Architecture Intel VT x added hardware support in the processor to improve the virtualization performance and robustness RTS Real Time Hypervisor support...

Page 46: ...Remarks Power Button Wakes unconditionally from S3 S5 Onboard LAN Event Device driver must be configured for Wake On LAN support SMBALERT Wakes unconditionally from S3 S5 PCI Express WAKE Wakes uncond...

Page 47: ...For information about the internal pull ups or pull downs implemented by the chip vendors refer to the respective chip s datasheet Table 10 Signal Tables Terminology Descriptions Term Description PU...

Page 48: ..._CK A68 PCIE_TX0 B68 PCIE_RX0 A14 GBE0_CTREF 1 B14 SMB_DAT A69 PCIE_TX0 B69 PCIE_RX0 A15 SUS_S3 B15 SMB_ALERT A70 GND FIXED B70 GND FIXED A16 SATA0_TX B16 SATA1_TX A71 eDP_TX2 LVDS_A0 B71 LVDS_B0 A17...

Page 49: ...B41 GND FIXED A96 TPM_PP B96 VGA_I2C_DAT A42 USB2 B42 USB3 A97 TYPE10 1 B97 SPI_CS A43 USB2 B43 USB3 A98 SER0_TX B98 RSVD 1 A44 USB_2_3_OC 3 B44 USB_0_1_OC 3 A99 SER0_RX B99 RSVD 1 A45 USB0 B45 USB1...

Page 50: ...GND C69 PEG_RX5 D69 PEG_TX5 C15 DDI1_PAIR6 1 D15 DDI1_CTRLCLK_AUX C70 GND FIXED D70 GND FIXED C16 DDI1_PAIR6 1 D16 DDI1_CTRLDATA_AUX 3 C71 PEG_RX6 D71 PEG_TX6 C17 RSVD 1 D17 RSVD 1 C72 PEG_RX6 D72 PEG...

Page 51: ...2 DDI3_PAIR1 D42 DDI2_PAIR1 C97 RVSD 1 D97 RSVD 1 C43 DDI3_PAIR1 D43 DDI2_PAIR1 C98 PEG_RX14 D98 PEG_TX14 C44 DDI3_HPD D44 DDI2_HPD C99 PEG_RX14 D99 PEG_TX14 C45 RSVD 1 D45 RSVD 1 C100 GND FIXED D100...

Page 52: ...0 PCIE_TX3 PCIE_TX3 A58 A59 PCI Express channel 3 Transmit Output differential pair O PCIE Supports PCI Express Base Specification Revision 3 0 PCIE_RX4 PCIE_RX4 B55 B56 PCI Express channel 4 Receive...

Page 53: ...RX7 PEG_RX7 PEG_RX8 PEG_RX8 PEG_RX9 PEG_RX9 PEG_RX10 PEG_RX10 PEG_RX11 PEG_RX11 PEG_RX12 PEG_RX12 PEG_RX13 PEG_RX13 PEG_RX14 PEG_RX14 PEG_RX15 PEG_RX15 C52 C53 C55 C56 C58 C59 C61 C62 C65 C66 C68 C69...

Page 54: ...D78 D79 D81 D82 D85 D86 D88 D89 D91 D92 D94 D95 D98 D99 D101 D102 PCI Express Graphics Transmit Output differential pairs Note Can also be used as PCI Express Transmit Output differential pairs 16 th...

Page 55: ...RLDATA if DDI1_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3 V PU 100 k 3 3V Bootstrap signal see note below Enable strap is already populated DDI1_DDC_AUX_SEL D34 Selects the function of DDI1_CTRLCL...

Page 56: ...I O PCIE I O OD 3 3 V PD 100 k DDI3_CTRLDATA_AUX 1 C37 Multiplexed with DP3_AUX and HDMI3_CTRLDATA DP AUX function if DDI3_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled...

Page 57: ...ATA C33 TMDS I2 C Control Data Multiplexed with DDI2_CTRLDATA_AUX I O OD 3 3 V PU 100 k 3 3 V Bootstrap signal see note below Enable strap is already populated TMDS3_CLK TMDS3_CLK C49 C50 TMDS Clock o...

Page 58: ...V DP1_AUX is a bootstrap signal see note below DP enable strap is already populated DP2_LANE3 DP2_LANE3 D49 D50 Uni directional main link for the transport of isochronous streams and secondary data Mu...

Page 59: ...DID access I O PCIE PD 100 k DP3_AUX 1 C37 Half duplex bi directional AUX channel for services such as link configuration or maintenance and EDID access I O PCIE PU 100 k 3 3 V DP3_AUX is a bootstrap...

Page 60: ...5 V PU 2k2 3 3 V Table 20 LVDS Signal Descriptions Signal Pin Description I O PU PD Comment LVDS_A0 LVDS_A0 LVDS_A1 LVDS_A1 LVDS_A2 LVDS_A2 LVDS_A3 LVDS_A3 A71 A72 A73 A74 A75 A76 A78 A79 LVDS Channel...

Page 61: ...tive low I O 3 3 V Table 22 USB 2 0 Signal Descriptions Signal Pin Description I O PU PD Comment USB0 B46 USB Port 0 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB0 B45 USB Port 0...

Page 62: ...open drain driver from a USB current monitor on the carrier board may drive this line low I 3 3 VSB PU 10 k 3 3 VSB USB0_HOST_ PRSNT B48 Module USB client may detect the presence of a USB host on USB...

Page 63: ...ent limited on the module In the case in which the reference is shorted to ground the current shall be limited to 250 mA or less REF Not connected GBE0_SDP A49 Gigabit Ethernet Controller 0 Software D...

Page 64: ...C serial interrupt I O 3 3 V PU 10 K 3 3 V ESPI Mode eSPI Master Chip Select Outputs driving Chip Select A low selects a particular eSPI slave for the transaction Each of the eSPI slaves is connected...

Page 65: ...1 These signals have special functionality during the reset process They may bootstrap some basic important functions of the module For more information refer to section 9 2 Bootstrap Signals Table 2...

Page 66: ...System Management Signal Descriptions Signal Pin Description I O PU PD Comment PWRBTN B12 Power button to bring system out of S5 soft off active on falling edge Note For proper detection assert a puls...

Page 67: ...se width of at least 16 ms I OD 3 3 V PU 100 k 3 3 VSB Note 1 Pins are protected on the module by a series schotty diode Therefore pull down resistor is required on the carrier board for proper logic...

Page 68: ...dules following the Type 2 6 Pinout standard The conga TS370 is based on the COM Express Type 6 pinout therefore the pins 0 and 1 are not connected and pin 2 is connected to GND TYPE2 TYPE1 TYPE0 X NC...

Page 69: ...for standby and suspend functions May be left unconnected if these functions are not used in the system design P VCC_RTC A47 Real time clock circuit power input Nominally 3 0V P GND A1 A11 A21 A31 A4...

Page 70: ...DDC_AUX_SEL is no connect I O PCIE HDMI1_CTRLDATA HDMI DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high I O OD 3 3 V DDI2_CTRLDATA_AUX C33 Multiplexed with DP2_AUX and HDMI2_CTRLDATA PU 100 k 3 3 V...

Page 71: ...I O cycles that are not positively decoded are forwarded to the PCI Bus not the LPC Bus Only specified I O ranges are forwarded to the LPC Bus In the congatec Embedded BIOS the following I O address r...

Page 72: ...erface 1 00h Note1 16h 01h Intel ME Interface 2 00h Note1 16h 02h ME IDE Redirection IDE R Interface 00h Note1 16h 03h ME Keyboard and Text KT Redirection 00h Note1 16h 04h Intel ME Interface 3 00h No...

Page 73: ...ort 7 Note 1 In the standard configuration the Intel Management Engine ME related devices are partly present or not present at all 2 The PCI Express Ports are visible only if a device is attached to t...

Page 74: ...Note If you do not have access to the restricted area of the congatec website contact your local congatec sales representative 11 1 Navigating the BIOS Setup Menu The BIOS setup menu shows the featur...

Page 75: ...www congatec com Note 1 Deprecated Caution The DOS command line tool is not officially supported by congatec and therefore not recommended for critical tasks such as firmware updates We recommend to...

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