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Signal
Pin # Description
I/O
PU/PD
Comment
DP
DP3_LANE2-
C46
C47
Uni-directional main link for the transport of isochronous streams and
secondary data
Multiplexed with DDI and DDI3_PAIR2-
O PCIE
DP
DP3_LANE1-
C42
C43
Uni-directional main link for the transport of isochronous streams and
secondary data
Multiplexed with DDI and DDI3_PAIR1-
O PCIE
DP
DP3_LANE0-
C39
C40
Uni-directional main link for the transport of isochronous streams and
secondary data
Multiplexed with DDI and DDI3_PAIR0-
O PCIE
DP3_HPD
C44
Detection of Hot Plug / Unplug and notification of the link layer
Multiplexed with DDI3_HPD
I 3.3 V
PD 100 kΩ
C36
Half-duplex bi-directional AUX channel for services such as link configuration
or maintenance and EDID access
I/O PCIE PD 100 kΩ
DP3_AUX-
1
C37
Half-duplex bi-directional AUX channel for services such as link configuration
or maintenance and EDID access
I/O PCIE PU 100 kΩ
3.3 V
DP3_AUX- is a bootstrap signal (see note below).
DP enable strap already populated
Note
1.
These signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For
more information refer to section 9.2 “Bootstrap Signals”.
Table 18 Embedded DisplayPort Signal Descriptions
Signal
Pin # Description
I/O
PU/PD
Comment
eDP_TX3-
eDP_TX2-
eDP_TX1-
eDP_TX0-
A81
A82
A71
A72
A73
A74
A75
A76
eDP differential pairs
AC coupled off
module.
eDP_VDD_EN
A77
eDP power enable
O 3.3 V
eDP_BKLT_EN
B79
eDP backlight enable
O 3.3 V
eDP_BKLT_CTRL
B83
eDP backlight brightness control
O 3.3 V
A83
eDP AUX+
AC coupled off
module
eDP_AUX-
A84
eDP AUX-
AC coupled off
module
eDP_HPD
A87
Detection of hot plug / unplug and notification of the link layer I 3.3 V
PD 100 kΩ
