ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
5.2.7.3
Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or
Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear
policy, both registers reading back the current enabled state of the corresponding interrupts. When an
interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the
interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until
cleared by reset or an exception return. Clearing the enable bit prevents new activations of the
associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to
enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading
back the current pended state of the corresponding interrupts. The Clear-Pending Register has no
effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
