ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 245 -
Revision 2.4
[15]
SPIENSTS
SPI Enable Bit Status (Read Only)
0 = Indicate the transmit control bit is disabled.
1 = Indicate the transfer control bit is active.
Note: The clock source of SPI controller logic is engine clock, it is asynchronous with the
system clock. In order to make sure the function is disabled in SPI controller logic, this bit
indicates the real status of SPIEN in SPI controller logic for user.
[14:13]
Reserved
Reserved.
[12]
RXTOIF
Receive Time-out Interrupt Status
0 = No receive FIFO time-out event.
1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over
64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode.
When the received FIFO buffer is read by software, the time-out status will be cleared
automatically.
Note: This bit will be cleared by writing 1 to itself.
[11]
RXOVIF
Receive FIFO Overrun Status
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be
set to 1.
Note: This bit will be cleared by writing 1 to itself.
[10]
RXTHIF
Receive FIFO Threshold Interrupt Status (Read Only)
0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting
value of RXTH.
1 = The valid data count within the receive FIFO buffer is larger than the setting value of
RXTH.
Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI controller will generate a SPI interrupt
request.
[9]
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
0 = Receive FIFO buffer is not full.
1 = Receive FIFO buffer is full.
[8]
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
0 = Receive FIFO buffer is not empty.
1 = Receive FIFO buffer is empty.
[7]
SLVURIF
Slave Mode Error 1 Interrupt Status (Read Only)
In Slave mode, transmit under-run occurs when the slave select line goes to inactive
state.
0 = No Slave mode error 1 event.
1 = Slave mode error 1 occurs.
[6]
SLVBEIF
Slave Mode Error 0 Interrupt Status (Read Only)
In Slave mode, there is bit counter mismatch with DWIDTH when the slave select line
goes to inactive state.
0 = No Slave mode error 0 event.
1 = Slave mode error 0 occurs.
Note: If the slave select active but there is no any serial clock input, the SLVBEIF also
active when the slave select goes to inactive state.
[5]
SLVTOIF
Slave Time-out Interrupt Status (Read Only)
When the Slave Select is active and the value of SLVTOCNT is not 0 and the serial clock
input, the slave time-out counter in SPI controller logic will be start. When the value of
time-out counter greater or equal than the value of SPI0_SSCTL.SLVTOCNT, during
before one transaction done, the slave time-out interrupt event will active.
0 = Slave time-out is not active.
1 = Slave time-out is active.
Note: If the DWIDTH is set 16, one transaction is equal 16 bits serial clock period.
