ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 383 -
Revision 2.4
SD ADC Control Register (SDADC_CTL)
Register
Offset
R/W
Description
Reset Value
SDADC_CTL
S0x0C R/W
SD ADC Control Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
RATESEL
Reserved
DMICEN
7
6
5
4
3
2
1
0
THIE
FIFOTH
FIFOBITS
DSRATE
Bits
Description
[31:12]
Reserved
Reserved.
[11]
RATESEL
Should be 0
[10:9]
Reserved
Reserved
[8]
DMICEN
Digital MIC Enable
1 = turn digital MIC function input from GPIO.
0 = keep SDADC function.
[7]
FIFOTHIE
FIFO Threshold Interrupt Enable
0 = disable interrupt whenever FIFO level exceeds that set in FIFOTH.
1 = enable interrupt whenever FIFO level exceeds that set in FIFOTH.
[6:4]
FIFOTH
FIFO Threshold:
Determines at what level the ADC FIFO will generate a interrupt.
Interrupt will be generated when number of words present in ADC FIFO is >
FIFOTH.
[3:2]
FIFOBITS
FIFO Data Bits Selection
0 = 32 bits
1 = 16 bits
2 = 8 bits
3 = 24 bits
[1:0]
DSRATE
Down Sampling Ratio
0 = reserved
1 = down sample X 16
2 = down sample X 32
3 = down sample X 64
