ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 322 -
Revision 2.4
I2S Clock Divider (I2S_CLKDIV)
Register
Offset
R/W
Description
Reset Value
I2S_CLKDIV
0x04
R/W
I2S Clock Divider Register
0x0000_0000
15
14
13
12
11
10
9
8
BCLKDIV
7
6
5
4
3
2
1
0
Reserved
MCLKDIV
Table 5-133 I2S Clock Divider Register (I2S_CLKDIV, address 0x400A_0004)
Bits
Description
[31:16]
Reserved
Reserved.
[15:8]
BCLKDIV
Bit Clock Divider
If I2S operates in master mode, bit clock is provided by I91200. Software can
program these bits to generate bit clock frequency for the desired sample rate.
For sample rate Fs, the desired bit clock frequency is:
F
BCLK
= Fs x Word_width_in_bytes x 16.
For example if Fs = 16kHz, and word width is 2-bytes (16bit) then desired bit clock
frequency is 512kHz.
The bit clock frequency is given by:
F
BCLK
= F
I2S_CLKDIV
/ (2x (1)).
Or,
BCLKDIV = F
I2S_CLKDIV
/ (2 x F
BCLK
) -1.
So if F
I2S_CLKDIV
= HCLK = 49.152MHz
, desired
F
BCLK
= 512kHz
then BCLKDIV = 47.
[7:3]
Reserved
Reserved.
[2:0]
MCLKDIV
Master Clock Divider
I91200can generate a master clock to synchronously drive an external audio device.
If MCLKDIV is set to 0, MCLK is the same as I2S_CLKDIV clock input, otherwise
MCLK frequency is given by:
F
MCLK
= F
I2S_CLKDIV
/ (2 x MCLKDIV).
Or,
MCLKDIV = F
I2S_CLKDIV
/ (2 x F
MCLK
).
If the desired MCLK frequency is 4.092MHz (= 256Fs) and Fs = 16kHz then
MCLKDIV = 6 @ F
I2S_CLKDIV
= 49.152MHz
.
