ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 264 -
Revision 2.4
[22]
TWOB
Two Bits Transfer Mode
1 = Enable two-bit transfer mode.
0 = Disable two-bit transfer mode.
Note that when enabled in master mode, MOSI data comes from
SPI1_TX0 and MOSI data from SPI1_TX1. Likewise SPI1_RX0 receives bit
stream from MISO0 and SPI1_RX1 from MISO1. Note that when enabled,
the setting of TXNUM must be programmed as 0x00
[21]
FIFO
FIFO Mode
0 = No FIFO present on transmit and receive buffer.
1 = Enable FIFO on transmit and receive buffer.
[20]
BYTEENDIAN
Byte Endian Reorder Function
This function changes the order of bytes sent/received to be least
significant physical byte first.
[19]
BYTESLEEP
Insert Sleep interval between Bytes
This function is only valid for 32bit transfers (TXBITLEN=0). If set then a
pause of (SLEEP+2) SCLK cycles is inserted between each byte
transmitted.
[18]
SLAVE
Master Slave Mode Control
0 = Master mode.
1 = Slave mode.
[17]
IE
Interrupt Enable
0 = Disable SPI Interrupt.
1 = Enable SPI Interrupt to CPU.
[16]
IF
Interrupt Flag
0 = Indicates the transfer is not finished yet.
1 = Indicates that the transfer is complete. Interrupt is generated to CPU if
enabled.
NOTE
: This bit is cleared by writing 1 to itself.
[15:12]
SLEEP
Suspend Interval (Master Only)
These four bits provide configurable suspend interval between two
successive transmit/receive transactions in a transfer. The suspend interval
is from the last falling clock edge of the current transaction to the first rising
clock edge of the successive transaction if CLKP
= 0. If CLKP
= 1, the
interval is from the rising clock edge to the falling clock edge. The default
value is 0x0. When
TXNUM = 00b, setting this field has no effect on
transfer except as determined by REORDER[0] setting. The suspend
interval is determined according to the following equation:
(SLEEP[3:0] + 2) * period of SCLK
[11]
CLKP
Clock Polarity
0 = SCLK idle low.
1 = SCLK idle high.
