ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 379 -
Revision 2.4
7.1.4.5
Peripheral DMA Request
Normal use of the SDADC is with PDMA. In this mode ADC requests PDMA service whenever data is
in FIFO. PDMA channel will copy this data to a buffer and alert the CPU when buffer is full. In this way
an entire buffer of data can be collected without any CPU intervention.
7.1.5
ADC Register Map
R
: read only,
W
: write only,
R/W
: both read and write,
C
: Only value 0 can be written
Register
Offset
R/W
Description
Reset Value
SDADC Base Address:
SDADC_BA = 0x400E_0000
SDADC_DAT
S0x00
R
SD ADC FIFO Data Read Register
0xxxxx_xxxx
SDADC_EN
S0x04
R/W
SD ADC Enable Register
0x0000_0000
SDADC_CLKDIV
S0x08
R/W
SD ADC Clock Divider Register
0x0000_0000
SDADC_CTL
S0x0C
R/W
SD ADC Control Register
0x0000_0000
SDADC_FIFOSTS
S0x10
R/W
SD ADC FIFO Status Register
0x0000_0002
SDADC_PDMACTL
S0x14
R/W
SD ADC PDMA Control Register
0x0000_0000
SDADC_CMPR0
S0x18
R/W
SD ADC Comparator 0 Control Register
0x0000_0000
SDADC_CMPR1
S0x1C
R/W
SD ADC Comparator 1 Control Register
0x0000_0000
SDADC_SDCHOP
S0x20
R/W
Sigma Delta Analog Block Control Register
0x001c_1021