ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
2. If the slave select active but there is no any serial clock input, the SLVBEIF also active when the
slave select goes to inactive state.
Slave Under-run and Slave Error 1 interrupts
In Slave mode, if there is no any data is written to the SPI0_TX register, the under-run event, TXUFIF
(SPI0_STATUS[19]) will active when the slave select active and the serial clock input this controller.
The SPI controller will issue an interrupt if the SLVUDRIEN is set to 1.
Under the previous condition, the Slave mode error 1, SLVURIF, SPI0_STATUS[7], will be set to 1
when SS goes to inactive state and transmit under-run occurs. The SPI controller will issue an interrupt
if the SLVUDRIEN, SPI0_SSCR[9], is set to 1.
Note: In SLV3WIRE mode, the slave select bus active all the time so that the user shall polling the
TXUFIF bit to know if there is transmit under-run event or not.
Receive Over-run interrupt
In Slave mode, if the receive FIFO buffer contains 8 unread data, the RXFULL flag will be set to 1 and
the RXOVIF will be set 1 if there is more serial data is received from SPIMOSI and the RXOVIF will be
set to 1 and follow-up data will be dropped. The SPI controller will issue an interrupt if the RXOVIEN,
SPI0_FIFOCTL[5], set to 1.
Receive FIFO time-out interrupt
In FIFO mode, there is a time-out function to inform user. If there is a received data in the FIFO and it is
not read by software over 64 SPI engine clock periods in Master mode or over 576 SPI engine clock
periods in Slave mode, it will send a time-out interrupt to the system if the time-out interrupt enable bit,
RXTOIEN, SPI0_FIFOCTL[4], is set to 1.
Transmit FIFO interrupt
In FIFO mode, if the valid data count of the transmit FIFO buffer is less than or equal to the setting
value of TXTH, the transmit FIFO interrupt flag will be set to 1. The SPI controller will generate a
transmit FIFO interrupt to the system if the transmit FIFO interrupt enable bit, SPI0_FIFOCTL[3], is set
to 1.
Receive FIFO interrupt
In FIFO mode, if the valid data count of the receive FIFO buffer is larger than the setting value of RXTH,
the receive FIFO interrupt flag will be set to 1. The SPI controller will generate a receive FIFO interrupt
to the system if the receive FIFO interrupt enable bit, SPI0_FIFOCTL[2], is set to 1.
5.9.4.14
3-Wire Mode
When the SLV3WIRE bit is set by software to enable the Slave 3-wire mode, the SPI controller can
work with no slave select signal in Slave mode. The SLV3WIRE bit only takes effect in Slave mode.
Only three pins, SPICLK, SPI0_MISO, and SPI0_MOSI, are required to communicate with a SPI
master. The SPISS pin can be configured as a GPIO. When the SLV3WIRE bit is set to 1, the SPI slave
will be ready to transmit/receive data after the SPIEN bit is set to 1.
5.9.4.15
2-Bit Mode
The SPI controller supports 2-bit Transfer mode when setting the TWOBIT bit (SPI0_CTL[16]) to 1. In
2-bit mode, the SPI controller performs full duplex data transfer. In other words, the 2-bit serial data can
be transmitted and received simultaneously.
For example, in Master mode, the first data written to the TX FIFO will be transmitted through
SPI0_MOSI0 and the second data written to the TX FIFO will be transmitted through the SPI0_MOSI1
pin. After transmission, the first read of RX FIFO will result in the data received from SPI0_MISO0 pin
and the second read the data received from SPI0_MISO1 pin.
In Slave mode, the first two data stored in the TX FIFO will be transmitted through the SPI0_MISO0 and
SPI0_MISO1 pin respectively. Concurrently, the RX FIFO will store the data received from the
