ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
5.10.4.15
Interrupt
The SPI controller can generate a CPU interrupt when data transfer is finished. When a transfer request
triggered by EN is finished, the interrupt flag (SPI_CTL.IF) will be set by hardware. If the SPI interrupt is
enabled (SPI1_CTL.IE) this will also generate a CPU interrupt. To clear the interrupt event flag,
software must write a ‘1’ to it.
5.10.4.16
FIFO Mode
The SPI controller supports a dual buffer mode when SPI_CTL.FIFO is set as 1. In normal mode,
software can only update the transmitted data when the current transmission is done. In FIFO mode,
the next transmitted data can be written into the SPI_TX buffer at any time when in master mode or the
EN bit is set in slave mode. This data will load into the transmit buffer when the current transmission
done.
After the FIFO bit is set, transmission is repeated automatically when the transmitted data is updated in
time and it will continue until this bit is cleared. When cleared, the transmission will finish when the
current transmission done. The user can also read the received data at any time before the next
transmission is complete, wherein the receive buffer will be updated with new received data. If transmit
data isn’t updated before the current transmission is done, the transaction will stop. The transmission
will resume automatically when transmit data is written into this buffer again.
Before the FIFO bit is set, the user can write first data into SPI1_TX buffer. Setting FIFO active will load
the first data into the current transmission buffer. A subsequent write to SPI_TX will load the TX FIFO
which will be loaded into the transmission buffer after the 1st transmission is done.
This function is also supported in slave mode. The EN must be set as 1 before the external serial clock
input and it will keep going until the FIFO is cleared.
The delay period between two transmissions is programmable. It is the same as the suspend interval
on SLEEP parameter.
5.10.4.17
Two Channel Mode
The SPI controller supports a two channel mode where data can be sent and received on alternate
MOSI1 and MISO1 lines concurrently with data on MOSI0 and MISO0. The data for this second
channel is the SPI1_RX1 and SPI1_TX1 buffers. Mode is enabled by setting the SPI_CTL.TWOB bit.
This mode is only available when TXNUM=0.
SPICLK
MOSIx0
MISOx0
Tx0[30]
Tx0[16]
Tx0[15]
Tx0[14]
LSB
Tx0[0]
MSB
Tx0[31]
Rx0[30]
Rx0[16]
Rx0[15]
Rx0[14]
LSB
Rx0[0]
MSB
Rx0[31]
CLKP=0
CLKP=1
SPI->SS
SS.LVL=1
SS.LVL=0
MOSIx1
MISOx1
Tx1[30]
Tx1[16]
Tx1[15]
Tx1[14]
LSB
Tx1[0]
MSB
Tx1[31]
Rx1[30]
Rx1[16]
Rx1[15]
Rx1[14]
LSB
Rx1[0]
MSB
Rx1[31]
Figure 5-61 Two Bits Transfer Mode
5.10.4.18
Variable Serial Clock Frequency
In master mode 16 bit transfers, the output of serial clock can be programmed as variable frequency
pattern if the Variable Clock Enable bit SPI1_CTL.VARCLKEN is enabled. The frequency pattern format
is defined in SP1I_VARCLK register. If the bit content of VARCLK is ‘0’ the output period for that bit is
