ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
5.3.3
Peripheral Clocks
Each peripheral has a selectable clock gate. The register CLK_APBCLK0 determines whether the
clock is active for each peripheral. In addition, the CLK_SLEEPCTL
register determines whether these
clocks remain on during M0 sleep mode. Certain peripheral clocks have selectable sources these are
controlled by the CLK_CLKSEL1 & CLK_CLKSEL2 register.
5.3.4
Power Management
The I91200 is equipped with a Power Management Unit (PMU) that implements a variety of power
saving modes. There are five levels of power control with increasing functionality (and power
consumption):
•
Level0 : Deep Power Down (DPD)
•
Level1 : Standby Power Down (SPD)
•
Level2: STOP
•
Level3 : Deep Sleep
•
Level4 : Sleep
•
Level5 : Normal Operation
Within each of these levels there are further options to optimize power consumption.
5.3.4.1
Level0: Deep Power Down (DPD)
Deep Power Down (DPD) is the lowest power state the device can obtain. In this state there is no
power provided to the logic domain and power consumption is only from the higher voltage chip supply
domain. All logic state in the Cortex-M0 is lost as is contents of all RAM. All IO pins of the device are in
a high impedance state. On a release from DPD the Cortex-M0 boots as if from a power-on reset.
There are certain registers that can be interrogated to allow software to determine that previous state
was a DPD state.
In DPD there are three ways to wake up the device:
1. A high to low transition on the WAKEUP pin.
2. A timed wakeup where the LIRC is configured active and reaches a certain count.
3. A power cycle of main chip supply triggering a POR event.
To assist software in determining previous state of device before a DPD, a one-byte register is
available CLK_DPDSTATE [7:0] that can be loaded with a value to be preserved before issuing a DPD
request.
To configure the device for DPD the user sets the following options:
•
CLK_PWRCTL.WKPINEN: If set to ‘1’ then the WAKEUP pin is disabled and will not wake up
the chip.
•
CLK_PWRCTL.LIRCDPDEN: If set to ‘1’ then the LIRC will power down in DPD. No timed
wakeup is possible.
•
CLK_WAKE10K.SELWKTMR: Each bit in this register will trigger a wakeup event after a
certain number of LIRC cycles.
When a WAKEUP event occurs the PMU will start the Cortex-M0 processor and execute the reset
vector. The condition that generated the WAKEUP event can be interrogated by reading the registers
CLK_PWRCTL.WKPINWKF, CLK_PWRCTL.TMRWKF and CLK_PWRCTL.PORWKF.
To enter the DPD state the user must set the register bit CLK_PWRCTL.DPDEN then execute a WFI
or WFE instruction. Note that when debug interface is active, device will not enter DPD. Also once
device enters DPD the debug interface will be inactive. It is possible that user could write code that
makes it impossible to activate the debug interface and reprogram device, for instance if device re-
