ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 464 -
Revision 2.4
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HWTRGCOND
External Trigger Condition
These two bits decide external pin STADC trigger event is level or edge. The signal must
be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state
for edge trigger.
00 = Low level.
01 = High level.
10 = Falling edge.
11 = Rising edge.
[5:4]
HWTRGSEL
Hardware Trigger Source Selection
00 = A/D conversion is started by external STADC pin.
Others = Reserved.
Software should disable TRGEN and SWTRG before change HWTRGSEL.
[3:2]
OPMODE
A/D Converter Operation Mode
00 = Single conversion.
01 = Reserved.
10 = Single-cycle scan.
11 = Continuous scan.
When changing the operation mode, software should disable SWTRG bit firstly.
[1]
ADCIE
A/D Interrupt Enable Bit
0 = A/D interrupt function Disabled.
1 = A/D interrupt function Enabled.
A/D conversion end interrupt request is generated if ADCIE bit is set to 1.
[0]
ADCEN
A/D Converter Enable Bit
0 = Disabled.
1 = Enabled.
Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable
A/D converter analog circuit for saving power consumption.
