ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 207 -
Revision 2.4
RTC Frequency Compensation Register (RTC_FREQADJ)
Register
Offset
R/W
Description
Reset Value
RTC_FREQADJ
0x008 R/W
RTC Frequency Compensation Register
0x0000_0700
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
INTEGER
7
6
5
4
3
2
1
0
Reserved
FRACTION
Table 5-80 RTC Frequency Compensation Register (RTC_FREQADJ, address 0x4000_8008).
Bits
Description
[31:12]
Reserved
Reserved.
[11:8]
INTEGER
Integer Part
Register should contain the value (INT(F
actual
) – 32761)
Ex: Integer part of detected value = 32772,.
RTC_FREQADJ.INTEGER = 32772-32761 = 11 (..1011b)
The range between 32761 and 32776
[7:6]
Reserved
Reserved.
[5:0]
FRACTION
Fractional Part
Formula = (fraction part of detected value) x 60.
Refer to
Table 5-76 RTC Frequency Compensation Example
or the examples.
Note: This register can be read back after the RTC enable is active.