ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 442 -
Revision 2.4
7.7
Biquad Filter (BIQ)
7.7.1
Overview and Features
A coefficient programmable 6-stage Biquad filter (12
th
-Order IIR filter) is available which can be used on
either SDADC path or DPWM path to further reduce unwanted noise or filter the signal. Each biquad filter
has the transfer function as
H(z)
and is implemented in Direct Form II Transpose structure as.
Upon power on reset or when the BIQ_CTL.DLCOEFF =1 is released, a set of default coefficients
b
n0
, b
n1
,
b
n2
, a
n1
, a
n2
(n = 1,2,3 which is the stage number of the filter) will be written to the coefficient RAM
automatically. And these coefficients can be over-written by the processor for different filter specifications.
Note that the fixed point coefficients have the format of 3.16 (19 bits) and are stored in the coefficient
RAM under normal operation. It takes 32 internal system clocks for the automatic write to finish when the
BIQ_CTL.DLCOEFF bit is released; it is important that the processor has enough delay before start the
coefficient programming or enabling biquad (BIQ_CTL.BIQEN). Attempting to program the coefficients
before the auto programming is done will result in unsuccessful programming. The default coefficient
setting is a low pass filter with 3db cut-off frequency with 16KHz Fs (Sample Rate) and 256 OSR
Biquad is released from reset by setting BIQ_CTL.DLCOEFF =1. After 32 clock cycles, processor can
setup other Biquad parameters or re-program coefficients before enabling filter.
The BIQ_CTL.PATHSEL register bit determines which path the BIQ is going to use. The default value is 0
which is the microphone ADC path, by setting this bit 1, the BIQ will be used in DPWM path.
If the BIQ is intended to be used in DPWM path, the BIQ can up sample the data rate by programming
BIQ_CTL.DPWMPUSR register which has default value at 1.
If the BIQ is intended to be used in ADC path, the BIQ can down sample the data rate by programming
BIQ_CTL.SDADCWNSR, register which has default value at 1.
The BIQ filter is in reset state in default. To use the BIQ function, the following sequence is
recommended:
1. Set BIQ_CTL.DLCOEFF bit. By releasing the reset, the filter controller will download default
coefficients automatically to the RAM.
2. Turn on the BIQ_CTL.PRGCOEFF bit if intending to change the coefficients. Otherwise skip to
next step.
3. Setup the BIQ operation sample rate by program DPWMPUSR or SRDIV register bits if
necessary.
4. Decide the SDADC or DPWM path to be used for the BIQ by programming PATHSEL, and turn
off PRGCOEFF bit (if it was turned on in step #2).
5. Setup BIQ stage (BIQ_CTL.STAGE), set “1” BIQ with 5 stages, set “0” BIQ with 6 stages.
6. Setup high pass filter on or off (BIQ_CTL.HPFON. If HPF is ON, the BIQ Stage automatically set
6 stages, one for HPF).
7. Turn on BIQ_CTL.BIQEN, BIQ will start filter function.
