ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 310 -
Revision 2.4
Baud Rate Divider Register (UARTn_BAUD)
Register
Offset
R/W
Description
Reset Value
UARTn_BAUD
U0x24 R/W
UART Baud Rate Divisor Register
0x0F00_0000
The baud rate generator takes the UART master clock UART_CLK and divides it to produce the baud
rate (bit rate) clock. The divider has two division stages controlled by BRD and EDIVM1 fields. These
are configured in three modes depending on the selections of BAUDM1 and BAUDM0. These modes
and the baud rate equations for them are described in Table 5-115 UART Baud Rate Equation.
31
30
29
28
27
26
25
24
Reserved
BAUDM1
BAUDM0
EDIVM1
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
BRD[15:0]
7
6
5
4
3
2
1
0
BRD[7:0]
Table 5-128 UART Baud Rate Divider Register (UARTn_BAUD, address 0x4005_0024)
Bits
Description
[31:30]
Reserved
Reserved.
[29]
BAUDM1
Divider X Enable
The baud rate equation is:
Baud Rate = UART_CLK / [ M * (BRD + 2) ] ; The default value of M is 16.
0 = Disable divider X ( M = 16).
1 = Enable divider X (M = 1, with EDIVM1
≥
8).
Refer to Table 5-116 UART Baud Rate Setting Table for more information.
NOTE: When in IrDA mode, this bit must disabled.
[28]
BAUDM0
Divider X Equal 1
0: M = 1, with restriction EDIVM1
≥
8.
1: M = 1, with restriction BRD[15:0]
≥
3.
Refer to Table 5-116 UART Baud Rate Setting Table for more information.
[27:24]
EDIVM1
Divider x
The baud rate divider M = 1.
[23:16]
Reserved
Reserved.
[15:0]
BRD
Baud Rate Divider
Refer to Table 5-116 UART Baud Rate Setting Table for more information.
