value initialization:
o
DIG_ANA(0)- Standard:
Absolute value initialization using a mix of the digital and analog
components (this is the default mode)
o
DIG(1) - Digital:
Only the digital component will be used for the absolute value
initialization.
o
SEK_SEL37(2) - Automatic:
Digital if ST bits > (Li 8); otherwise standard (criterion applies
with HIPERFACE SEKL-37 encoders)
o
SSI_180(3) - Same as Standard, except:
In the case of SSI, the quadrant alignment of the digital value relative
to the analog Sin/Cos tracks is not the same as with EnDat, but is
instead offset by 180 degrees relative to EnDat, i.e. in the “natural Q
alignment” for the digital value relative to the tracks.
l
P 1900[0] - ENC_ETS
= ETS mode, electronic nameplate
The parameter ENC_ETS supports what is referred to as the “Moog
electronic rating plate” for HIPERFACE encoders. If this parameter is set to
SCAN(0), the motor’s commutation offset will be read from the encoder’s
OEM memory and copied to
P 349 - CON_FM_MConOffset
, but only if this
offset can be unambiguously identified in the encoder (encoder memory
scanning). If the parameter is set to NEVER(0) instead, this functionality will
be disabled.
6.5.4.2.5 SSI absolute value interface
If P 540[0] - ENC_CH1_Abs = SSI(1), which is the normal setting, the absolute SSI
encoder position will be read once during the initialization phase; after this, the
cyclical encoder position will be acquired based on the Sin/Cos incremental
component.
The parameters for the SSI interface are described in Section "SSI (cyclical) X7" on
page 69, as are the differences in using the SSI interface with the “cyclical” method
and “one-time reading” method.
MOOG
ID No.: CB40859-001 Date: 11/2020
MSD Servo Drive - Device Help
67
6 Encoder
If P 540[0] - ENC_CH1_Abs = SSI_CONT(4), which is a special case, the absolute
SSI encoder position will be read once during the initialization phase; after this, the
cyclical encoder position will be acquired based on the Sin/Cos incremental
component. The reason this is a special case is that the SSI clock will continue to be
cyclically output on the SSI clock lines, in contrast to the SSI(1) setting. This means
that the connected SSI encoder will continue to cyclically deliver position data on the
SSI data lines. However, once the SSI data is read once, the controller will not
evaluate any additional SSI data. -- This functionality can be used in the special
case if the 485 system is implemented as a bus system on the encoder side so that a
third 485 node (e.g. a controller) can “also listen in to” the SSI position data as an
SSI clock slave.
6.5.4.2.6 EnDat absolute value interface
If P 540[0] - ENC_CH1_Abs = ENDAT(2), the absolute EnDat encoder position will
be read once during the initialization phase; after this, the cyclical encoder position
will be acquired based on the Sin/Cos incremental component.
The parameters for the EnDat interface are described in Section "EnDat
(cyclical) X7" on page 61, as are the differences in using the EnDat interface with the
“cyclical” method and “one-time reading” method.
6.5.4.2.7 HIPERFACE absolute value interface
If P 540[0] - ENC_CH1_Abs = HIPER(3), the absolute HIPERFACE encoder position
will be read once during the initialization phase; after this, the cyclical encoder
position will be acquired based on the Sin/Cos incremental component. The
HIPERFACE interface will
not be used as an alternative to cyclical encoder position
acquisition.
HIPERFACE functionality: After an SW reset is carried out from the HIPERFACE
encoder as the very first step, the ID byte, referred to as the “TypeKey”, will be read
from the encoder and interpreted: If it is equal to FFh, the data for Lines, MultiT and
