3.6.3.4. Register File RAM Blocks
1. Use a
WRCTL
instruction to set
ECCINJ.RF
to
INJS
or
INJD
(as desired).
2. Execute any instruction that writes any register except
R0
.
3. Use a
RDCTL
instruction to ensure that the value of
ECCINJ.RF
is
NOINJ
.
4. Use an instruction to read the desired register from rA such as
OR rd, r0, rx
where
rx
is the register written in the previous step. This action triggers the ECC
error.
5. Use an instruction to read the desired register from rB such as
OR rd, rx, r0
where
rx
is the register written in the previous step.
3.6.3.5. Data Cache Tag RAM
1. Use a
LOAD
instruction from a data address to get the line in the cache. The line
should be clean.
2. Use a
WRCTL
instruction to set
ECCINJ.DCTAG
to
INJS
or
INJD
.
3. Use a
STORE
instruction from a data address mapped to that line. The
STORE
instruction should hit in the data cache and write the tag RAM to set the dirty bit.
4. The ECC error is injected when the tag RAM is written.
5. Use a
RDCTL
instruction to ensure the value of
ECCINJ.DCTAG
is
NOINJ
. Before
the
RDCTL
, use a
FLUSHP
instruction to avoid the RAW hazard on
ECCINJ
.
6. Do another
LOAD
or
STORE
instruction to the same line.
7. The ECC error should be triggered on this second
LOAD
/
STORE
instruction.
3.6.3.6. Data Cache Data RAM (Clean Line)
1. Use a
FLUSHDA
instruction to ensure the line isn’t in the data cache.
2. Use a
LOAD
instruction to load a clean data cache line.
3. Use a
WRCTL
instruction to set
ECCINJ.DCDAT
field to
INJS
or
INJD
.
4. Use a
LOAD
instruction to an address in the data cache line to inject the error.
5. Use a
RDCTL
instruction to ensure the values of the field written by the
WRCTL
to
ECCINJ
is
NOINJ
. Before the
RDCTL
, use a
FLUSHP
instruction to avoid the RAW
hazard on
ECCINJ
.
6. Use a
LOAD
instruction from the same address.
7. The ECC error should be triggered on the
LOAD
instruction.
3.6.3.7. Data Cache Data RAM (Dirty Line)
1. Use a
LOAD
instruction to load a data cache line.
2. Use a
WRCTL
instruction to set
ECCINJ.DCDAT
field to
INJS
or
INJD
(as desired).
3. Use a
STORE
instruction to an address in the data cache line.
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
72
