6. Nios II Processor Versions
Each release of the Nios II Embedded Design Suite (EDS) introduces improvements to
the Nios II processor, the software development tools, or both. This chapter catalogs
the history of revisions to the Nios II processor; it does not track revisions to
development tools, such as the Nios II Software Build Tools (SBT).
Improvements to the Nios II processor might affect:
•
Features of the Nios II architecture—An example of an architecture revision is
adding instructions to support floating-point arithmetic.
•
Implementation of a specific Nios II core—An example of a core revision is
increasing the maximum possible size of the data cache memory for the Nios II/f
core.
•
Features of the JTAG debug module—An example of a JTAG debug module revision
is adding an additional trigger input to the JTAG debug module, allowing it to halt
processor execution on a new type of trigger event.
Intel FPGA implements Nios II revisions such that code written for an existing Nios II
core also works on future revisions of the same core.
6.1. Nios II Versions
The number for any version of the Nios II processor is determined by the version of
the Nios II EDS.
Table 76.
Document Revision History
Version
Release Date
Notes
14.0
January 2015
Initial release of the Nios II processor.
6.2. Architecture Revisions
Architecture revisions augment the fundamental capabilities of the Nios II
architecture, and affect all Nios II cores. A change in the architecture mandates a
revision to all Nios II cores to accommodate the new architectural enhancement. For
example, when Intel FPGA adds a new instruction to the instruction set, Intel FPGA
consequently must update all Nios II cores to recognize the new instruction.
Table 77.
Nios II Architecture Revisions
Version
Release Date
Notes
14.0
January 2015
Initial release of the Nios II processor architecture.
NII-PRG | 2018.04.18
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