4. Perform an instruction/data access to cause the hardware to read the TLB entry
(copied into uTLB) and the ECC decoder should detect the ECC error at this time.
Alternatively, initiate a software read of the TLB (by writing
TLBMISC.RD
to 1).
5. If a software read was initiated, the
TLBMISC.EE
field should be set to 1 on any
instruction after the
WRCTL
that triggered the software read.
6. If a hardware read was initiated, the ECC error should be triggered on the first
instruction after the hardware read.
3.7. Exception Processing
Exception processing is the act of responding to an exception, and then returning, if
possible, to the pre-exception execution state.
All Nios II exceptions are precise. Precise exceptions enable the system software to
re-execute the instruction, if desired, after handling the exception.
3.7.1. Terminology
Intel FPGA Nios II documentation uses the following terminology to discuss exception
processing:
•
Exception—a transfer of control away from a program’s normal flow of execution,
caused by an event, either internal or external to the processor, which requires
immediate attention.
•
Interrupt—an exception caused by an explicit request signal from an external
device; also: hardware interrupt.
•
Interrupt controller—hardware that interfaces the processor to interrupt request
signals from external devices.
•
Internal interrupt controller—the nonvectored interrupt controller that is integral
to the Nios II processor. The internal interrupt controller is available in all revisions
of the Nios II processor.
•
Vectored interrupt controller (VIC)—an Intel-provided external interrupt controller.
•
Exception (interrupt) latency—The time elapsed between the event that causes the
exception (assertion of an interrupt request) and the execution of the first
instruction at the handler address.
•
Exception (interrupt) response time—The time elapsed between the event that
causes the exception (assertion of an interrupt request) and the execution of
nonoverhead exception code, that is, specific to the exception type (device).
•
Global interrupts—All maskable exceptions on the Nios II processor, including
internal interrupts and maskable external interrupts, but not including
nonmaskable interrupts.
•
Worst-case latency—The value of the exception (interrupt) latency, assuming the
maximum disabled time or maximum masked time, and assuming that the
exception (interrupt) occurs at the beginning of the masked/disabled time.
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
74
