When individual external interrupts have dedicated shadow register sets, the Nios II
processor supports fast interrupt handling with no overhead for saving register
contents. To take full advantage of fast interrupt handling, system software must set
up certain conditions. With the following conditions satisfied, ISRs need not save and
restore register contents on entry and exit:
•
Automatic nested interrupts are enabled.
•
Each interrupt is assigned to a dedicated shadow register set.
•
All interrupts with the same RIL are assigned to dedicated shadow register sets.
•
Multiple interrupts with different RILs can be assigned to a single shadow register
set. However, with multiple register sets, you must not allow the RILs assigned to
one shadow register set to overlap the RILs assigned to another register set.
The following tables demonstrate the validity of register set assignments when
preemption within a register set is enabled.
Table 45.
Example of Illegal RIL Assignment
RIL
Register Set 1
Register Set 2
1
IRQ0
2
IRQ1
3
IRQ2
4
IRQ3
5
IRQ4
6
IRQ5
7
IRQ6
Table 46.
Example of Legal RIL Assignment
RIL
Register Set 1
Register Set 2
1
IRQ0
2
IRQ1
3
IRQ3
4
IRQ2
5
IRQ4
6
IRQ5
7
IRQ6
Note:
Noninterrupt exception handlers must always save and restore the register contents,
because they run in the normal register set.
Multiple interrupts can share a register set, with some loss of performance. There are
two techniques for sharing register sets:
•
Set
status.RSIE
to 0. When an ISR is running in a given register set, the
processor does not take any maskable interrupt assigned to the same register set.
Such interrupts must wait for the running ISR to complete, regardless of their
interrupt level.
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
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