5.4.5. Instruction Performance
The Nios II/e core dispatches a single instruction at a time, and the processor waits
for an instruction to complete before fetching and dispatching the next instruction.
Because each instruction completes before the next instruction is dispatched, branch
prediction is not necessary. This greatly simplifies the consideration of processor stalls.
Maximum performance is one instruction per six clock cycles. To achieve six cycles,
the Avalon-MM instruction master port must fetch an instruction in one clock cycle. A
stall on the Avalon-MM instruction master port directly extends the execution time of
the instruction.
Table 75.
Instruction Execution Performance for Nios II/e Core
Instruction
Cycles
Normal ALU instructions (e.g.,
add
,
cmplt
)
6
All branch,
jmp
,
jmpi
,
ret
,
call
,
callr
6
trap
,
break
,
eret
,
bret
,
flushp
,
wrctl
,
rdctl
,
unimplemented
6
All load word
6 + Duration of Avalon-MM read transfer
All load halfword
9 + Duration of Avalon-MM read transfer
All load byte
10 + Duration of Avalon-MM read transfer
All store
6 + Duration of Avalon-MM write transfer
All shift, all rotate
7 to 38
All other instructions
6
Combinatorial custom instructions
6
Multicycle custom instructions
6
5.4.6. Exception Handling
The Nios II/e core supports the following exception types:
•
Internal hardware interrupt
•
Software trap
•
Illegal instruction
•
Unimplemented instruction
5.4.7. JTAG Debug Module
The Nios II/e core supports the JTAG debug module to provide a JTAG interface to
software debugging tools. The JTAG debug module on the Nios II/e core does not
support hardware breakpoints or trace.
5. Nios II Core Implementation Details
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