4. Use a
RDCTL
instruction to ensure the values of the field written by the
WRCTL
to
ECCINJ
is
NOINJ
. Before the
RDCTL
, use a
FLUSHP
instruction to avoid the RAW
hazard on
ECCINJ
.
5. Either use a
LOAD
instruction from the same address or trigger a writeback of the
dirty line (e.g.
FLUSHDA
instruction)
6. The ECC error should be triggered on the
LOAD
instruction unless it is only
detected during the writeback of a dirty line. In the writeback of a dirty line case,
the ECC error is triggered an undefined number of instructions later.
3.6.3.8. Data Cache Victim Line Buffer RAM
1. Use a
LOAD
instruction to load a data cache line.
2. Use a
WRCTL
instruction to set
ECCINJ.DCWB
field to
INJS
or
INJD
(as desired).
3. Use a
STORE
instruction to an address in the data cache line.
4. Use a
RDCTL
instruction to ensure the values of the field written by the
WRCTL
to
ECCINJ
is
NOINJ
. Before the
RDCTL
, use a
FLUSHP
instruction to avoid the RAW
hazard on
ECCINJ
.
5. Either use a
LOAD
instruction from the same address or trigger a writeback of the
dirty line (e.g.
FLUSHDA
instruction)
6. The ECC error should be triggered on the
LOAD
instruction unless it is only
detected during the writeback of a dirty line. In the writeback of a dirty line case,
the ECC error is triggered an undefined number of instructions later.
3.6.3.9. DTCMs
1. Use a
WRCTL
instruction to set the
ECCINJ.DTCM
field to
INJS
or
INJD
for the
desired
DTCM
.
2. Use a
STW
instruction to write an address in the
DTCM
.
3. Use a
RDCTL
instruction to ensure the value of the field written by the
WRCTL
to
ECCINJ
is
NOINJ
.
4. Use a
LOAD
instruction from the same address in the
DTCM
.
5. The ECC error should be triggered on the
LOAD
instruction.
3.6.3.10. MMU TLB RAM
1. Use a
WRCTL
instruction to set
ECCINJ.TLB
to
INJS
or
INJD
.
2. Use a
WRCTL
instruction to write a TLB entry. The ECC error will be injected at this
time and any associated uTLB entry will be flushed.
3. Use a
RDCTL
instruction to ensure the value of
ECCINJ.TLB
is
NOINJ
.
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
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