Figure 8.
Nios II Platform Designer Caches and Memory Interfaces Tab
4.3.1. Instruction Cache
The Instruction cache parameters provide the following options for the Nios II/f core:
•
Size—Specifies the size of the instruction cache. Valid sizes are from 512 bytes to
64 KBytes, or None.
Choosing None disables the instruction cache. The Avalon-MM instruction master
port from the Nios II processor will still available. In this case, you must include a
tightly-coupled instruction memory.
•
Add burstcount signal to instruction_master —The Nios II processor can fill
its instruction cache lines using burst transfers. Usually you enable bursts on the
processor's instruction master when instructions are stored in DRAM, and disable
bursts when instructions are stored in SRAM.
Bursting to DRAM typically improves memory bandwidth, but might consume
additional FPGA resources. Be aware that when bursts are enabled, accesses to
slaves might go through additional hardware (called burst adapters) which might
decrease your f
MAX
.
When the Nios II processor transfers execution to the first word of a cache line,
the processor fills the line by executing a sequence of word transfers that have
ascending addresses, such as 0, 4, 8, 12, 16, 20, 24, 28.
However, when the Nios II processor transfers execution to an instruction that is
not the first word of a cache line, the processor fetches the required (or “critical”)
instruction first, and then fills the rest of the cache line. The addresses of a burst
increase until the last word of the cache line is filled, and then continue with the
first word of the cache line. For example, with a 32-byte cache line, transferring
control to address 8 results in a burst with the following address sequence: 8, 12,
16, 20, 24, 28, 0, 4.
4. Instantiating the Nios II Processor
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