The
status.IL
field controls what level of external maskable interrupts can be
serviced. The processor services a maskable interrupt only if its requested interrupt
level is greater than
status.IL
.
An ISR can make run-time adjustments to interrupt nesting by manipulating
status.IL
. For example, if an ISR is running at level 5, to temporarily allow pre-
emption by another level 5 interrupt, it can set
status.IL
to 4.
To enable all external interrupts, set
status.IL
to 0. To disable all external
interrupts, set
status.IL
to 63.
3.7.13.3. Masking Interrupts with the Internal Interrupt Controller
The
ienable
register controls the handling of internal hardware interrupts. Each bit
of the
ienable
register corresponds to one of the interrupt inputs,
irq0
through
irq31
. A value of one in bit n means that the corresponding
irq
n interrupt is
enabled; a bit value of zero means that the corresponding interrupt is disabled.
Refer to the "Exception Processing" section of this chapter for more information.
An ISR can adjust
ienable
so that IRQs of equal or lower priority are disabled. Refer
to the "Handling Nested Exceptions" section of this chapter for more information.
Related Information
•
Handling Nested Exceptions
on page 94
•
Exception Processing
on page 74
3.7.13.4. Returning From Interrupt and Instruction-Related Exceptions
The
eret
instruction is used to resume execution at the pre-exception address.
You must ensure that when an exception handler modifies registers, they are restored
when it returns. This can be taken care of in either of the following ways:
•
In the case of ISRs, if the EIC interface and shadow register sets are
implemented, and the ISR has a dedicated register set, no software action is
required. The Nios II processor returns to the previous register set when it
executes
eret
, which restores the register contents.
•
For details, refer to the "Nested Exceptions with an External Interrupt Controller"
section of this chapter.
•
In the case of noninterrupt exceptions, for ISRs in a system with the internal
interrupt controller, and for ISRs without a dedicated shadow register set, the
exception handler must save registers on entry and restore them on exit. Saving
the register contents on the stack is a typical, re-entrant implementation.
Note:
It is not necessary to save and restore the exception temporary (
et
or
r24
) register.
When executing the
eret
instruction, the processor performs the following tasks:
1. Restores the previous contents of
status
as follows:
3. Programming Model
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Nios II Processor Reference Guide
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