1. Introduction
We have ended development of new Nios
®
II Classic processor features with the
Intel
®
Quartus
®
Prime 14.0 release. New features are implemented only in the Nios II
processor core. Although the Classic processor remains supported, we recommend
that you use the Nios II core for future designs.
This handbook describes the Nios II processor from a high-level conceptual description
to the low-level details of implementation. The chapters in this handbook describe the
Nios II processor architecture, the programming model, and the instruction set. The
Nios II processor is only availabe in the Intel Quartus Prime 14.1 release and above.
This handbook assumes you have a basic familiarity with embedded processor
concepts. You do not need to be familiar with any specific Intel FPGA technology or
with Intel FPGA development tools. This handbook limits discussion of hardware
implementation details of the processor system. The Nios II processors are designed
for Intel FPGA devices, and so this handbook does describe some FPGA
implementation concepts. Your familiarity with FPGA technology provides a deeper
understanding of the engineering trade-offs related to the design and implementation
of the Nios II processor.
This chapter introduces the Intel FPGA Nios II embedded processor family and
describes the similarities and differences between the Nios II processor and traditional
embedded processors.
Related Information
Nios II Processor webpage
1.1. Nios II Processor System Basics
The Nios II processor is a general-purpose RISC processor core with the following
features:
•
Full 32-bit instruction set, data path, and address space
•
32 general-purpose registers
•
Optional shadow register sets
•
32 interrupt sources
•
External interrupt controller interface for more interrupt sources
•
Single-instruction 32 × 32 multiply and divide producing a 32-bit result
•
Dedicated instructions for computing 64-bit and 128-bit products of multiplication
•
Optional floating-point instructions for single-precision floating-point operations
•
Single-instruction barrel shifter
NII-PRG | 2018.04.18
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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