Interrupts can be re-enabled by writing one to the
PIE
bit, thereby allowing the
current ISR to be interrupted. Typically, the exception routine adjusts
ienable
so that
IRQs of equal or lower priority are disabled before re-enabling interrupts.
Refer to "Handling Nested Exceptions” for more information.
Related Information
Handling Nested Exceptions
on page 94
3.7.9.4. Exceptions and Processor Status
The Nios II Processor Status After Taking Exception Table lists all changes to the Nios
II processor state as a result of nonbreak exception processing actions performed by
hardware. For systems with an MMU,
status.EH
indicates whether or not exception
processing is already in progress. When
status.EH
= 1, exception processing is
already in progress and the states of the exception registers are preserved to retain
the original exception states.
Table 44.
Nios II Processor Status After Taking Exception
Processor Status Register
or Field
System Status Before Taking Exception
External Interrupt Asserted (19)
Internal Interrupt Asserted or Noninterrupt Exception
status.EH==1 (34)
status.EH==0
status.EH==1
status.EH==0
TLB
Miss (36)
No TLB Miss
RRS==0 (
35)
RRS!=0
RRS==0
RRS!=0
TLB
Permission
Violation (36)
No TLB
Permission
Violation
pteaddr.VPN
(20)
No change
VPN (21)
No change
status.PRS
(
35
)
No change
status.CRS
(
35
) (
37
)
No change
pc
RHA
General
exception
vector (22)
Fast TLB
exception
vector (23)
General exception vector(
35
)
sstatus
(24)(
38
)
No change
status
(
37
)
(25)
No change
estatus
(
38
)
No change
status
(
37
)
No change
status
(
37
)
ea
No change
return address (26)
No change
return address
tlbmisc.D
(
34
)
No change
(27)
continued...
(19) If the Nios II processor does not have an EIC interface, external interrupts do not occur.
(20) If the Nios II processor does not have an MMU, this register is not implemented.
(21) The VPN of the address triggering the exception
(22) Invokes the general exception handler
(23) Invokes the fast TLB miss exception handler
(24) If the Nios II processor does not have shadow register sets, this register is not implemented.
(25)
sstatus.SRS
is set to 1 if RRS is not equal to
status.CRS
.
(26) The address following the instruction being executed when the exception occurs
(27) Set to 1 on a data access exception, set to 0 otherwise
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
91
