Many Nios II systems have simpler requirements where minimal system software or a
small-footprint operating system (such as the Intel FPGA
®
hardware abstraction library
(HAL) or a third party real-time operating system) is sufficient. Such software is
unlikely to function correctly in a hardware system with an MMU-based Nios II
processor. Do not include an MMU in your Nios II system unless your operating system
requires it.
Note:
The Intel FPGA HAL and HAL-based real-time operating systems do not support the
MMU.
If your system needs memory protection, but not virtual memory management, refer
to Memory Protection Unit section.
Related Information
Memory Protection Unit
on page 43
3.2.2. Memory Management
Memory management comprises two key functions:
•
Virtual addressing—Mapping a virtual memory space into a physical memory space
•
Memory protection—Allowing access only to certain memory under certain
conditions
3.2.2.1. Virtual Addressing
A virtual address is the address that software uses. A physical address is the address
which the hardware outputs on the address lines of the Avalon
®
bus. The Nios II MMU
divides virtual memory into 4-KB pages and physical memory into 4-KB frames.
The MMU contains a hardware translation lookaside buffer (TLB). The operating
system is responsible for creating and maintaining a page table (or equivalent data
structures) in memory. The hardware TLB acts as a software managed cache for the
page table. The MMU does not perform any operations on the page table, such as
hardware table walks. Therefore the operating system is free to implement its page
table in any appropriate manner.
There is a 20 bit virtual page number (VPN) and a 12 bit page offset.
Table 7.
MMU Virtual Address Fields
Bit Fields
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Virtual Page Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Virtual Page Number
Page Offset
As input, the TLB takes a VPN plus a process identifier (to guarantee uniqueness). As
output, the TLB provides the corresponding physical frame number (PFN).
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
38
