Exception
Type
Available
Cause
Address
Vector
Double TLB miss (data)
Instruction-
related
MMU
12
pteaddr.VPN
,
badaddr
(data
address)
General
exception
TLB permission violation
(read)
Instruction-
related
MMU
14
pteaddr.VPN
,
badaddr
(data
address)
General
exception
TLB permission violation
(write)
Instruction-
related
MMU
15
pteaddr.VPN
,
badaddr
(data
address)
General
exception
MPU region violation (data)
Instruction-
related
MPU
17
badaddr
(data
address)
General
exception
Bus Data Region Violation
M core
24
badaddr
(data
address)
General
exception
ECC Data Error
ECC and (data cache
OR DTCM)
21
badaddr
(data
address)
General
exception
Related Information
•
Requested Handler Address
on page 80
•
General-Purpose Registers
on page 45
3.7.3. Exception Latency
Exception latency specifies how quickly the system can respond to an exception.
Exception latency depends on the type of exception, the software and hardware
configuration, and the processor state.
3.7.3.1. Interrupt Latency
The interrupt controller can mask individual interrupts. Each interrupt can have a
different maximum masked time. The worst-case interrupt latency for interrupt i is
determined by that interrupt’s maximum masked time, or by the maximum disabled
time, whichever is greater.
3.7.4. Reset Exceptions
When a processor reset signal is asserted, the Nios II processor performs the following
steps:
1. Sets
status.RSIE
to 1, and clears all other fields of the
status
register.
2. Invalidates the instruction cache line associated with the reset vector.
3. Begins executing the reset handler, located at the reset vector.
(15)
It is possible for any instruction fetch to cause this exception.
(16)
Refer to the Nios II General-Purpose Registers Table for descriptions of the
ea
and
ba
registers.
(17)
For a description of the requested handler address, refer to the Requested Handler Address
section of this chapter.
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
77
