Note:
All partitions except the user partition in the "Virtual Memory Partition" table are
supervisor-only partitions.
Each partition has a specific size, purpose, and relationship to the TLB:
•
The 512-MB I/O partition provides access to peripherals.
•
The 512-MB kernel partition provides space for the operating system kernel.
•
The 1-GB kernel MMU partition is used by the TLB miss handler and kernel
processes.
•
The 2-GB user partition is used by application processes.
I/O and kernel partitions bypass the TLB. The kernel MMU and user partitions use the
TLB. If all software runs in the kernel partition, the MMU is effectively disabled.
3.2.3.2. Physical Memory Address Space
The 4-GB physical memory is divided into low memory and high memory. The lowest
½ GB of physical address space is low memory. The upper 3½ GB of physical address
space is high memory.
Figure 4.
Division of Physical Memory
0x1FFFFFFF
0x00000000
0.5 GByte Low Memory
3.5 GByte High Memory
0xFFFFFFFF
0x20000000
Accessed directly or via TLB
Accessed only via TLB
High physical memory can only be accessed through the TLB. Any physical address in
low memory (29-bits or less) can be accessed through the TLB or by bypassing the
TLB. When bypassing the TLB, a 29-bit physical address is computed by clearing the
top three bits of the 32-bit virtual address.
Note:
To function correctly, the base physical address of all exception vectors (reset, general
exception, break, and fast TLB miss) must point to low physical memory so that
hardware can correctly map their virtual addresses into the kernel partition. The Nios
II Processor parameter editor in Platform Designer prevents you from choosing an
address outside of low physical memory.
3.2.3.3. Data Cacheability
Each partition has a rule that determines the default data cacheability property of
each memory access. When data cacheability is enabled on a partition of the address
space, a data access to that partition can be cached, if a data cache is present in the
system. When data cacheability is disabled, all access to that partition goes directly to
3. Programming Model
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Nios II Processor Reference Guide
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