Byte-enable signals on the master port specify which of the four byte-lane(s) to write
during store operations. Load and store operations can complete in a single clock cycle
when the data master port is connected to zero-wait-state memory.
Note:
Nios II only supports a fixed 32-byte linesize for data cache.
The Nios II architecture supports on-chip cache memory for improving average data
transfer performance when accessing slower memory. Refer to the "Cache Memory"
section of this chapter for details.
The Nios II architecture supports tightly-coupled memory, which provides guaranteed
low-latency access to on-chip memory. Refer to "Tightly-Coupled Memory" section of
this chapter for details.
Related Information
•
Cache Memory
on page 27
•
Tightly-Coupled Memory
on page 29
2.6.1.4. Shared Memory for Instructions and Data
Usually the instruction and data master ports share a single memory that contains
both instructions and data. While the processor core has separate instruction and data
buses, the overall Nios II processor system might present a single, shared instruction/
data bus to the outside world. The outside view of the Nios II processor system
depends on the memory and peripherals in the system and the structure of the
system interconnect fabric.
The data and instruction master ports never cause a gridlock condition in which one
port starves the other. For highest performance, assign the data master port higher
arbitration priority on any memory that is shared by both instruction and data master
ports.
2.6.2. Cache Memory
The Nios II architecture supports cache memories on both the instruction master port
(instruction cache) and the data master port (data cache). Cache memory resides on-
chip as an integral part of the Nios II processor core. The cache memories can
improve the average memory access time for Nios II processor systems that use slow
off-chip memory such as SDRAM for program and data storage.
The instruction and data caches are enabled perpetually at run-time, but methods are
provided for software to bypass the data cache so that peripheral accesses do not
return cached data. Cache management and cache coherency are handled by
software. The Nios II instruction set provides instructions for cache management.
2.6.2.1. Configurable Cache Memory Options
The cache memories are optional. The need for higher memory performance (and by
association, the need for cache memory) is application dependent. Many applications
require the smallest possible processor core, and can trade-off performance for size.
2. Processor Architecture
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
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