Reset vector offset specifies the location of the reset vector relative to the memory
module’s base address. Platform Designer calculates the physical address of the reset
vector when you modify the memory module, the offset, or the memory module’s
base address. In Platform Designer, Reset vector displays the read-only, calculated
address. The address is always a physical address, even when an MMU is present.
Note:
Platform Designer provides an Absolute option, which allows you to specify an
absolute address in Reset vector offset. Use an absolute address when the memory
storing the reset handler is located outside of the processor system and subsystems of
the processor system.
For information about reset exceptions, refer to the Programming Model chapter of the
Nios II Processor Reference Handbook.
Related Information
Programming Model
on page 36
4.2.2. Exception Vector
Parameters in this section select the memory module where the general exception
vector (exception address) resides, and the location of the general exception vector.
The general exception vector cannot be configured until your system memory
components are in place.
The Exception vector memory list, which includes all memory modules mastered by
the Nios II processor, selects the exception vector memory module. In a typical
system, select a low-latency memory module for the exception code.
Exception vector offset specifies the location of the exception vector relative to the
memory module’s base address. Platform Designer calculates the physical address of
the exception vector when you modify the memory module, the offset, or the memory
module’s base address. In Platform Designer, Exception vector displays the read-
only, calculated address.. The address is always a physical address, even when an
MMU is present.
Note:
Platform Designer provides an Absolute option, which allows you to specify an
absolute address in Exception vector offset. Use an absolute address when the
memory storing the exception handler is located outside of the processor system and
subsystems of the processor system.
For information about exceptions, refer to the Programming Model chapter of the Nios
II Processor Reference Handbook.
Related Information
Programming Model
on page 36
4.2.3. Fast TLB Miss Exception Vector
The fast TLB miss exception vector is a special exception vector used exclusively by
the MMU to handle TLB miss exceptions. Parameters in this section select the memory
module where the fast TLB miss exception vector (exception address) resides, and the
location of the fast TLB miss exception vector. The fast TLB miss exception vector
cannot be configured until your system memory components are in place.
4. Instantiating the Nios II Processor
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