Bit Fields
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
A
B
IMM16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IMM16
0x0c
8.5.6. beq
Instruction
branch if equal
Operation
if (rA == rB)
then PC ← PC + 4 + σ(IMM16)
else PC ← PC + 4
Assembler Syntax
beq rA, rB, label
Example
beq r6, r7, label
Description
If rA == rB, then
beq
transfers program control to the
instruction at label. In the instruction encoding, the offset
given by IMM16 is treated as a signed number of bytes
relative to the instruction immediately following
beq
. The
two least-significant bits of IMM16 are always zero, because
instruction addresses must be word-aligned.
Exceptions
Misaligned destination address
Instruction Type
I
Instruction Fields
A
= Register index of operand rA
B
= Register index of operand rB
IMM16
= 16-bit signed immediate value
Bit Fields
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
A
B
IMM16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IMM16
0x26
8.5.7. bge
Instruction
branch if greater than or equal signed
Operation
if ((signed) rA >= (signed) rB)
then PC ← PC + 4 + σ(IMM16)
else PC ← PC + 4
Assembler Syntax
bge rA, rB, label
Example
bge r6, r7, top_of_loop
Description
If (signed) rA >= (signed) rB, then
bge
transfers program
control to the instruction at label. In the instruction
encoding, the offset given by IMM16 is treated as a signed
number of bytes relative to the instruction immediately
continued...
8. Instruction Set Reference
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
178
