•
Nios II Core Implementation Details
on page 121
3.8.1.1. Virtual Address Aliasing
A virtual address alias occurs when two virtual addresses map to the same physical
address. When an MMU and caches are present and the caches are larger than a page
(4 KB), the operating system must prevent illegal virtual address aliases. Because the
caches are virtually-indexed and physically-tagged, a portion of the virtual address is
used to select the cache line. If the cache is 4 KB or less in size, the portion of the
virtual address used to select the cache line fits with bits 11:0 of the virtual address
which have the same value as bits 11:0 of the physical address (they are untranslated
bits of the page offset). However, if the cache is larger than 4 KB, bits beyond the
page offset (bits 12 and up) are used to select the cache line and these bits are
allowed to be different than the corresponding physical address.
For example, in a 64-KB direct-mapped cache with a 16-byte line, bits 15:4 are used
to select the line. Assume that virtual address
0x1000
is mapped to physical address
0xF000
and virtual address
0x2000
is also mapped to physical address
0xF000
. This
is an illegal virtual address alias because accesses to virtual address
0x1000
use line
0x1 and accesses to virtual address
0x2000
use line 0x2 even though they map to the
same physical address. This results in two copies of the same physical address in the
cache. With an n-byte direct-mapped cache, there could be n/4096 copies of the same
physical address in the cache if illegal virtual address aliases are not prevented. The
bits of the virtual address that are used to select the line and are translated bits (bits
12 and up) are known as the color of the address. An operating system avoids illegal
virtual address aliases by ensuring that if multiple virtual addresses map the same
physical address, the virtual addresses have the same color. Note though, the color of
the virtual addresses does not need to be the same as the color as the physical
address because the cache tag contains all the bits of the PFN.
3.9. Instruction Set Categories
This section introduces the Nios II instructions categorized by type of operation
performed.
3.9.1. Data Transfer Instructions
The Nios II architecture is a load-store architecture. Load and store instructions
handle all data movement between registers, memory, and peripherals. Memories and
peripherals share a common address space. Some Nios II processor cores use
memory caching and/or write buffering to improve memory bandwidth. The
architecture provides instructions for both cached and uncached accesses.
Table 47.
Wide Data Transfer Instructions
Instruction
Description
ldw
stw
The
ldw
and
stw
instructions load and store 32-bit data words from/to memory. The effective address is the sum
of a register's contents and a signed immediate value contained in the instruction. Memory transfers can be
cached or buffered to improve program performance. This caching and buffering might cause memory cycles to
occur out of order, and caching might suppress some cycles entirely.
Data transfers for I/O peripherals should use
ldwio
and
stwio
.
ldwio
stwio
ldwio
and
stwio
instructions load and store 32-bit data words from/to peripherals without caching and buffering.
Access cycles for
ldwio
and
stwio
instructions are guaranteed to occur in instruction order and are never
suppressed.
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
100
