instruction or data through the tightly-coupled memory interface. Software accesses
tightly-coupled memory with the usual load and store instructions, such as
ldw
or
ldwio
.
Accessing tightly-coupled memory bypasses cache memory. The processor core
functions as if cache were not present for the address span of the tightly-coupled
memory. Instructions for managing cache, such as
initd
and
flushd
, do not affect
the tightly-coupled memory, even if the instruction specifies an address in tightly-
coupled memory.
When the MMU is present, tightly-coupled memories are always mapped into the
kernel partition and can only be accessed in supervisor mode.
5.2.5. Memory Management Unit
The Nios II/f core provides options to improve the performance of the Nios II MMU.
For information about the MMU architecture, refer to the Programming Model chapter
of the Nios II Processor Reference Handbook.
Related Information
Programming Model
on page 36
5.2.5.1. Micro Translation Lookaside Buffers
The translation lookaside buffer (TLB) consists of one main TLB stored in on-chip RAM
and two separate micro TLBs (μTLB) for instructions μITLB) and data (μDTLB) stored
in LE-based registers.
The TLBs have a configurable number of entries and are fully associative. The default
configuration has 6 μDTLB entries and 4 μITLB entries. The hardware chooses the
least-recently used μTLB entry when loading a new entry.
The μTLBs are not visible to software. They act as an inclusive cache of the main TLB.
The processor firsts look for a hit in the μTLB. If it misses, it then looks for a hit in the
main TLB. If the main TLB misses, the processor takes an exception. If the main TLB
hits, the TLB entry is copied into the μTLB for future accesses.
The hardware automatically flushes the μTLB on each TLB write operation and on a
wrctl
to the
tlbmisc
register in case the process identifier (PID) has changed.
5.2.6. Memory Protection Unit
The Nios II/f core provides options to improve the performance of the Nios II MPU.
For information about the MPU architecture, refer to the Programming Model chapter
of the Nios II Processor Reference Handbook.
Related Information
Programming Model
on page 36
5. Nios II Core Implementation Details
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