clears the cache line regardless of whether the addressed
data is currently cached. This process comprises the
following steps:
• Compute the effective address specified by the sum of rA
and the signed 16-bit immediate value.
• Identify the data cache line associated with the
computed effective address. Each data cache effective
address comprises a
tag
field and a
line
field. When
identifying the line,
initd
ignores the
tag
field and only
uses the
line
field to select the data cache line to clear.
• Skip comparing the cache line tag with the effective
address to determine if the addressed data is currently
cached. Because
initd
ignores the cache line tag,
initd
flushes the cache line regardless of whether the
specified data location is currently cached.
• Skip checking if the data cache line is dirty. Because
initd
skips the dirty cache line check, data that has
been modified by the processor, but not yet written to
memory is lost.
• Clear the valid bit for the line.
If the Nios II processor core does not have a data cache,
the
initd
instruction performs no operation.
Usage
Use
initd
after processor reset and before accessing data
memory to initialize the processor’s data cache. Use
initd
with caution because it does not write back dirty data. By
contrast, refer to “flushd flush data cache line”, “flushda
flush data cache address”, and “initda initialize data cache
address” for other cache-clearing options. Intel recommends
using
initd
only when the processor comes out of reset.
For more information on data cache, refer to the Cache and
Tightly Coupled Memory chapter of the Nios II Software
Developer’s Handbook.
Exceptions
Supervisor-only instruction
Instruction Type
I
Instruction Fields
A
= Register index of operand rA
IMM16
= 16-bit signed immediate value
Bit Fields
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
A
0
IMM16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IMM16
0x33
Related Information
•
Cache and Tightly-Coupled Memory
•
flushda
on page 199
•
initda
on page 203
•
flushd
on page 198
8. Instruction Set Reference
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
202
