Usage
Use
flushda
to write dirty lines back to memory only if the
addressed memory location is currently in the cache, and
then flush the cache line. By contrast, refer to “flushd flush
data cache line”, “initd initialize data cache line”, and “initda
initialize data cache address” for other cache-clearing
options.
For more information on the Nios II data cache, refer to the
Cache and Tightly Coupled Memory chapter of the Nios II
Software Developer’s Handbook.
Exceptions
Supervisor-only data address
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
Instruction Type
I
Instruction Fields
A
= Register index of operand rA
IMM16
= 16-bit signed immediate value
Bit Fields
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
A
0
IMM16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IMM16
0x1b
Related Information
•
Cache and Tightly-Coupled Memory
•
initda
on page 203
•
initd
on page 201
•
flushd
on page 198
8.5.47. flushi
Instruction
flush instruction cache line
Operation
Flushes the instruction cache line associated with address
rA.
Assembler Syntax
flushi rA
Example
flushi r6
Description
Ignoring the tag,
flushi
identifies the instruction cache
line associated with the byte address in rA, and invalidates
that line.
If the Nios II processor core does not have an instruction
cache, the
flushi
instruction performs no operation.
For more information about the data cache, refer to the
Cache and Tightly Coupled Memory chapter of the Nios II
Software Developer’s Handbook.
Exceptions
None
Instruction Type
R
Instruction Fields
A
= Register index of operand rA
8. Instruction Set Reference
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
200
