Instruction
Cycles
Penalties
Divide
Late result
Shift/rotate (with hardware multiply using embedded multipliers)
1
Late result
Shift/rotate (with hardware multiply using LE-based multipliers)
2
Late result
Shift/rotate (without hardware multiply present)
1 to 32
Late result
All other instructions
1
For Multiply and Divide, the number of cycles depends on the hardware multiply or
divide option. Refer to "Arithmetic Logic Unit" and "Instruction and Data Caches" s for
details.
In the default Nios II/f configuration, instructions
trap, break, eret, bret,
flushp, wrctl, wrprs
require four clock cycles. If any of the following options are
present, they require five clock cycles:
•
MMU
•
MPU
•
Division exception
•
Misaligned load/store address exception
•
EIC port
•
Shadow register sets
Related Information
•
Data Cache
on page 126
•
Instruction and Data Caches
on page 125
•
Arithmetic Logic Unit
on page 123
5.2.9. Exception Handling
The Nios II/f core supports the following exception types:
•
Hardware interrupts
•
Software trap
•
Illegal instruction
•
Unimplemented instruction
•
Supervisor-only instruction (MMU or MPU only)
•
Supervisor-only instruction address (MMU or MPU only)
•
Supervisor-only data address (MMU or MPU only)
•
Misaligned data address
•
Misaligned destination address
•
Division error
•
Error-correcting code (ECC)
•
Fast translation lookaside buffer (TLB) miss (MMU only)
5. Nios II Core Implementation Details
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
131
