3.4.3.1. The sstatus Register
The value in the
sstatus
register preserves the state of the Nios II processor during
external interrupt handling. The value of
sstatus
is undefined at processor reset.
Some bits are exclusively used by and available only to certain features of the
processor.
The
sstatus
register is physically stored in general-purpose register
r30
in each
shadow register set. The normal register set does not have an
sstatus
register, but
each shadow register set has a separate
sstatus
register.
Table 40.
sstatus Control Register Fields
Bit Fields
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SRS
Reserved
RSIE
NMI
PRS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CRS
IL
IH
EH
U
PIE
Table 41.
sstatus Control Register Field Descriptions
Bit
Description
Access
Reset
Available
SRS
(13)
SRS
is the switched register set bit. The
processor sets
SRS
to 1 when an external
interrupt occurs, if the interrupt required the
processor to switch to a different register set.
Read/Write
Undefined
EIC interface
and shadow
register sets
only
RSIE
RSIE
is the register set interrupt-enable bit.
When set to 1, this bit allows the processor to
service external interrupts requesting the
register set that is currently in use. When set
to 0, this bit disallows servicing of such
interrupts.
Read/Write
Undefined
(
14
)
NMI
NMI
is the nonmaskable interrupt mode bit.
The processor sets
NMI
to 1 when it takes a
nonmaskable interrupt.
Read/Write
Undefined
(
14
)
PRS
(
14
)
Read/Write
Undefined
(
14
)
CRS
(
14
)
Read/Write
Undefined
(
14
)
IL
(
14
)
Read/Write
Undefined
(
14
)
IH
(
14
)
Read/Write
Undefined
(
14
)
EH
(
14
)
Read/Write
Undefined
(
14
)
U
(
14
)
Read/Write
Undefined
(
14
)
PIE
(
14
)
Read/Write
Undefined
(
14
)
(13)
If the EIC interface and shadow register sets are not present,
SRS
always reads as 0, and the
processor behaves accordingly.
(14)
Refer to the status Control Register Field Descriptions Table
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
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