flushing the pipeline as needed (either by using a
flushp
instruction or a
wrctl
instruction to a register that does flush the pipeline). Because a context switch
typically requires reprogramming the MPU regions for the new thread, flushing the
pipeline on each
wrctl
instruction would create unnecessary overhead.
3.5.2. MPU Initialization
Your system software must provide a data structure that contains the region
information described in the "Memory Regions" section of this chapter for each active
thread. The data structure ideally contains two 32-bit values that correspond to the
mpubase
and
mpuacc
register formats.
The MPU is disabled on system reset. Before enabling the MPU, Intel FPGA
recommends initializing all MPU regions. Enable desired instruction and data regions
by writing each region’s attributes to the
mpubase
and
mpuacc
registers as described
in the "MPU Region Read and Write Operations" section of this chapter. You must also
disable unused regions. When using region size, clear
mpuacc.MASK
to zero. When
using limit, set the
mpubase.BASE
to a nonzero value and clear
mpuacc.LIMIT
to
zero.
Note:
You must enable at least one instruction and one data region, otherwise unpredictable
behavior might occur.
To perform a context switch, use a
wrctl
to write a zero to the
PE
field of the
config
register to disable the MPU, define all MPU regions from the new thread’s data
structure, and then use another
wrctl
to write a one to
config.PE
to enable the
MPU.
Define each region using the pair of
wrctl
instructions described in the "MPU Region
Read and Write Operations" section of this chapter. Repeat this dual
wrctl
instruction
sequence until all desired regions are defined.
Related Information
•
MPU Region Read and Write Operations
on page 68
•
Memory Regions
on page 43
3.5.3. Debugger Access
The debugger can access all MPU-related control registers using the normal
wrctl
and
rdctl
instructions. During debugging, the Nios II ignores the MPU, effectively
temporarily disabling it.
3.6. Working with ECC
3.6.1. Enabling ECC
The ECC is disabled on system reset. Before enabling the ECC, initialize the Nios II
RAM blocks to avoid spurious ECC errors.
3. Programming Model
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Nios II Processor Reference Guide
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